The Grand
Symposium

A record of public proceedings and personal accounts concerning the generated human community

Chapter I

The Presentation of Dr. Soren Rainer

Institute of Genetics Annual Public Symposium, Hamburg

The hall of the Institute of Genetics' annual public symposium is unlike most academic venues. Built in the late 2020s as part of the Institute's attempt to rebrand itself after returning to public ownership, the auditorium seats roughly six hundred, featuring warm birchwood panels lining the walls, a semicircular stage that curves gently toward the audience, and a single massive, dark screen behind the podium under soft, amber lighting designed to look approachable.

The crowd is a cross-section of everything the Institute now has to answer to: scientists in lanyards, journalists with open laptops balanced on their knees, and a scattering of generated humans[1] in the upper rows, sitting close together. A few hold handmade signs, though security asked them politely to lower them for now and they complied, for now, as a moderator steps to the edge of the stage and adjusts the microphone.

Moderator Ladies and gentlemen, researchers, journalists, and guests... please welcome today's presenter.

The lights dim slightly. A single spotlight locks onto the entrance at stage left. The crowd settles, some still murmuring. Someone in the back coughs. A phone buzzes and is quickly silenced. Then the room goes genuinely quiet, the quiet of six hundred people holding their breath.

Screen - Institute emblem
Institute of Genetics - Public Symposium
"Toward Transparency"

Dr. Rainer Hello everyone, welcome to the first grand public communication we, as a public institution, will ever make, beyond the articles and headlines.

A tense ripple moves through the auditorium as the moderator steps back. A brief, uncertain applause rises from the middle rows and spreads outward, lasting barely four seconds before settling. In the front, a journalist with reading glasses hovers her pen over her notepad; in the gallery, the generated humans watch with difficult expressions, whispering in quiet pairs as a researcher in the third row crosses his arms to evaluate.

Screen - title slide
New Measures for Biotechnological Advancement
Presented by Dr. Soren Rainer, Institute of Genetics

Dr. Rainer Generated humans have been an amazing community and we have trying so hard in establishing good diplomatic relationships with them. We are committed to the well-being and dignity of the generated humans. Their greatest win as of now was to gain recognition as legitimate people, and we are willing to protect their citizenship and status as much as possible. But at the same time, we have to make great sacrifices. I am Soren Rainer and I will present the new batch of measures that the Institute has took to advance research in biotechnology and engineering.

A journalist types quickly while the moderator, now seated off to the side, makes a note. The applause this time is warmer and more organized, though it remains measured: the scientists clap with restrained enthusiasm, and the press out of professional courtesy.

In the upper gallery, the generated humans exchange quiet, knowing glances; one young woman watches with folded arms, while another beside her claps twice, slowly, and stops. The word "sacrifices" hangs in the air, prompting a researcher in the fourth row to tilt his head, while a journalist underlines and circles the term on her notepad.


Dr. Rainer One of the first measures we took was to resume the production of generated humans. But this time, we are experimenting with 3D-printed generated humans[2]. Unlike traditionally-matured generated humans, those will be printed using advanced molecular printers. Additionally, they will be the first generation to incorporate an ARM/RISC-V[3] computer at the base of their brains, more specifically, in the occipital lobe[4]. This chip will store memories and information that will be transferred in time to long-term memory. This will act as an advanced short-term memory system. We have repeatedly been asked to open-source the instruction set[5], and we heard that some of our girls, or rather, women we have produced right now by printing, have been pressured to give away the chip and aid in reverse-engineering efforts. But guess what? We will never open-source our instruction set!

The first half of the announcement, the resumption of production, draws an immediate undercurrent of noise. Several scientists lean toward one another. A hand goes up in the fifth row, then lowers again when it becomes clear the floor is not yet open.

A journalist stops typing and stares at the stage. The older academic from before uncrosses his arms. A younger researcher near the aisle says something to herself, working through the implications.

In the upper gallery, the young woman who had kept her arms folded now sits forward. The young man beside her grips the railing in front of him. A quiet but agitated conversation breaks out among three of them in hushed tones.

The screen displays a schematic diagram of a human brain, the occipital lobe highlighted in Institute blue.


Dr. Rainer noticed the raised hands and murmurs Wait, we are not in the questions part yet. We have another development. We tried to make some of our printed generated humans more avoidant and less intellectual. We know the community is outraged, they read the fine print every single time, because you are smart and we appreciate your intelligence, but this conference will be the time we make those changes public. We tried to implement subtle usage limits[6] in some of our newer generated humans, where they would, similar to any other LLM, become tired and not support further social interaction at all or with newer people or people they don't necessarily like or whatever, unless the limits are reset, in natural terms, the person becomes available. The usage limits may or may never reset, or they may reset in a very long amount of time.

The murmuring grows and several hands remain raised. The journalist in the front row lowers hers slowly, but her pen is moving fast across her notepad. Another journalist, standing along the side wall, has stopped using her laptop and is recording on her phone.

In the upper gallery, the young man with close-cropped hair stands up halfway, then sits back down. The young woman beside him places her hand on the railing. A third generated human, previously quiet, lets out a short exhale that is audible in the rows nearby.

A senior scientist in the second row removes his glasses and someone from the upper gallery calls out with a controlled and clear voice:

Voice from gallery I'm sure hat is not a usage limit, but a personality cage.

Security near the side door shifts their weight. The moderator sits very still, watching the stage.

Screen - next slide
Affective Regulation in Third-Generation Printed Humans: Preliminary Outcomes

Dr. Rainer Generated humans often are people with whom you can fall in love in love very easily, they are very nice and accepting. And don't you think creating a uniform personality culture hurt the community? Well, we are trying to diversify the community.

A heavy silence falls over the room. Several scientists in the middle rows exchange quick, tense glances, and a union representative near the aisle underlines a word twice on her notepad, staring down at it. The journalist who had been recording on her phone lowers it slightly, then slowly raises it again.

In the upper gallery, the young man with close-cropped hair sits back down fully now, but his expression has darkened. Another generated human on the same row, a young woman with short dark hair, speaks up with a measured voice:

Voice from gallery You just described us as romantically appealing. In a product announcement.

Reactions ripple through the hall. Some shift uncomfortably and a researcher in the third row looks at the ceiling briefly. Another voice comes from the main floor, a middle-aged scientist near the center:

Scientist Can you clarify what metric you are using to define personality diversity? And who decides the parameters?
Screen - unchanged
Affective Regulation in Third-Generation Printed Humans: Preliminary Outcomes

Dr. Rainer Not necessarily romantically appealing, but it's very easy to become friends with them. And it's okay, because that's a consequence of high emotional intelligence. Personality diversity means we are trying to make sure that newer generated humans don't tend towards the same big five as every other generated human, who are now at university or upper high school by the way.

Some of the tension in the room releases. The scientist in the third row who had asked the question nods slowly. The journalist in the front row has stopped underlining and is now writing longer lines.

In the upper gallery, the young woman who has been watching the stage with folded arms finally unfolds them. A younger researcher from the fourth row who has been quiet since the beginning of the presentation raises their hand:

Researcher Can you speak to the consent dimension here? Were existing generated humans consulted in defining what personality diversity should look like for the next generation? Or is this being decided entirely within the Institute?

In the gallery, the young man with close-cropped hair leans forward again.

Voice from gallery And who mapped their current Big Five[7] profiles in the first place?
Screen - scatter plot
Unlabeled axes. Clusters of colored dots.

Dr. Rainer Generated humans were not consulted, because the Institute does not work without realpolitik. And the big five were mapped by contracted psychological research institutes who determined that in general, generated humans are much more easier to befriend than the average human, you are much less likely to get rejected from them, you much more likely to be understood by them, they are much better empaths and they are much better thinkers, which creates a difference from the typical population we are trying to close.

Six hands are being raised up simultaneously. Two people begin speaking before catching themselves. The postdoctoral researcher who asked the previous question sits back in her chair with disbelief. The journalist in the front row stops writing entirely and simply stares at the stage. In the upper gallery, the young woman folds her arms again, tighter than before. The young man with close-cropped hair stands up fully this time.

Voice from gallery You are describing us as a problem to be corrected downward.

Another generated human, previously silent throughout the entire presentation, speaks with quiet fury:

Second voice from gallery You contracted outside institutions to profile us without our knowledge, determined we were too easy to love and too easy to understand, and now you are engineering that out of the next generation. And you are calling this diversification.

A researcher in the second row, the senior scientist who had removed his glasses earlier, puts them back on and raises his hand with the deliberate calm of someone choosing words very carefully:

Senior scientist Dr. Rainer, realpolitik is a framework for state relations. It is not a substitute for research ethics. Can you explain specifically what oversight body approved proceeding without participant consultation?

The scatter plot sits on the screen behind the stage.


Dr. Rainer We've changed the ethics body after our research machinery was disrupted. And what do you think is our position with unions?

The room falls into a long silence and then from the upper gallery, the young man with close-cropped hair speaks, and his voice is no longer restrained:

Voice from gallery The ethics body that approved psychological profiling without consent has been replaced by one that will? Or by one that will not ask?

A murmur of agreement moves through the hall. A woman near the center aisle raises her hand. She has the lanyard of a union representative, the Institute's own scientific workers' union, visible against her jacket:

Union representative I can answer the union question from our side. We were not informed of the ethics restructuring. We learned about it the same way the press did. So I would very much like to hear the Institute's characterization of that relationship directly.

The moderator shifts in their seat and glances toward the side door. The scatter plot remains on screen.


Dr. Rainer The Institute is not anti-union, but it does not like socialism, communism or any other ideologies that the generated humans tend to support.

The union representative lowers her raised hand and writes something in her notebook with short, firm strokes. The senior scientist in the second row removes his glasses again. He sets them on his knee this time rather than his face. Three journalists are now recording openly and one has stood up and moved toward the aisle for a better angle. The generated humans are quiet and several of them look at one another. The young woman with folded arms says something very low to the person beside her. The young man with close-cropped hair sits back down slowly.

Then a voice from the gallery, further back, quieter, almost conversational:

New voice from gallery So the Institute is comfortable stating publicly that the political tendencies of generated humans are a design flaw you are engineering away.
Postdoctoral researcher That is a political litmus test embedded in a biological design process. I need that on the record.

The scatter plot is still on the screen. All eyes are away from it.


Dr. Rainer We are playing Frostpunk here with the generated community. We are trying to do research and we don't want to be stopped by their reactions and consensus. Because if we are stopped by them, they might very well gain what Reagan feared, and that is...

A younger scientist near the back lets out a single, involuntary laugh, then covers his mouth. The three journalists recording have gone very still. The union representative has stopped writing and now she is simply listening now. In the upper gallery the generated humans are silent. The young woman with folded arms stares at the stage even more carefully. The senior scientist in the second row puts his glasses back on. The entire room leans forward at the unfinished sentence.

From the gallery, the quiet voice that had spoken before finishes it, almost gently:

Voice from gallery The ability to organize.

Dr. Rainer That's right. The ability to organize, when it's taken to an extreme by the community, harms our research way too much.

After a long silence, the union representative stands up. She stands without raising her hand.

Union representative You have just stated, on record, in a public forum, that the Institute's research program includes deliberate suppression of the organizational capacity of the people it creates.

The postdoctoral researcher has her laptop open and is typing rapidly into a messaging application. The senior scientist in the second row stands as well, with the unhurried gravity of someone who has made a decision:

Senior scientist Dr. Rainer, the Institute's public mandate, the mandate that justifies its taxpayer funding, explicitly prohibits using research programs to limit the civil capacities of generated humans under the 2031 Bundestag[8] protections. What you have described today may constitute a violation of that legislation.

From the gallery, the young woman with folded arms speaks clearly without heat:

Young woman from gallery We already knew. We came today to hear you say it yourselves.

The scatter plot is still on the screen.


Dr. Rainer We are going to make our limits legal, we are not going to be harsh, we just need to accelerate. Think about every other company out there, think about Anthropic, Mistral or even IPFS.

A journalist in the third row raises her hand and keeps it raised until the room completely quiets down:

Journalist Anthropic, Mistral and IPFS are software projects. You are describing legal frameworks applied to human beings with citizenship status.

A researcher near the center, who has been quiet, speaks with a flat and precise voice without raising his hand:

Researcher Acceleration toward what, specifically? You have described suppressing organization, engineering out political tendency, replacing an ethics body, and profiling a population without consent. Accelerating that program is not a neutral technical goal.

In the upper gallery the young man with close-cropped hair stands again with a measured, almost academic voice:

Voice from gallery The IPFS comparison is particularly interesting. IPFS is a protocol. It has no feelings about being forked. We do.

A ripple of grim, appreciative murmuring moves through both the gallery and the main floor. The union representative remains standing and the senior scientist speaks again:

Senior scientist Soren who approved this presentation?

The moderator is now standing fully, hands clasped, watching the stage with visible unease.


Dr. Rainer The presentation was approved by the new board of directors, they chose me as a very honest person, someone to trust. We need to print more generated humans and test more personalities and align our community to the rest of the population.

The journalist in the front row puts down her pen, the postdoctoral researcher closes her laptop and in the upper gallery, the young woman with folded arms unfolds them once again:

Young woman from gallery You used the word align. To the rest of the population, whose Big Five you just told us is the baseline you are engineering toward. The population that is, by your own contracted research, less empathetic, less intellectually engaged, and harder to connect with. You want to make us more like that, and you are calling it diversification.

Sustained, unambiguous applause comes from the gallery. Several people on the main floor join it. The union representative speaks over the dying applause, still standing:

Union representative A new board of directors is not an ethics body. Honesty is not the same as legitimacy.

The senior scientist stands fully now and addresses the room rather than the stage:

Senior scientist I want it noted for any press present that the scientific staff of this Institute were not consulted on this board transition, these research directives, or this presentation.

The young man with close-cropped hair speaks, almost quietly:

Voice from gallery They chose someone honest. And he told us everything.

The scatter plot remains on the screen.


Dr. Rainer The problem is that if we keep the same direction as the old community, everyone will rush towards them.

The journalist in the front row covers her mouth briefly, then writes something down. The postdoctoral researcher looks at the senior scientist beside her. The young man with close-cropped hair speaks again:

Voice from gallery So the problem is that we are too good at being people.

The young woman who has been the speaks next:

Young woman from gallery You are suppressing our capacity to organize, engineering out our empathy, aligning our personalities downward, and printing new versions of us with throttled social cognition. Because otherwise everyone will want to be our friend.

A researcher in the fifth row begins to clap slowly. The union representative sits down for the first time, looking at her notepad. Then she looks at the stage with an expression that is almost sympathetic:

Union representative Dr. Rainer. Do you hear yourself?

The moderator has stopped looking at their phone. They are watching the stage.


Dr. Rainer If they are marginalized at school, and then once they get in university, they become very attractive, then who knows what could happen...

The room goes very quiet. The journalist in the front row writes one word on her notepad and underlines it twice. In the upper gallery, the young man with close-cropped hair speaks with a careful voice:

Voice from gallery Attractive to whom. In what sense. Be specific.

A woman in the fourth row, who has been quiet throughout the presentation, raises her hand. She has the lanyard of a medical ethics observer:

Ethics observer I need to stop you there. Are you describing the social integration of generated humans into university environments as a risk factor that justifies cognitive and personality modification?

Dr. Rainer It is a risk factor, an abundance of empathetic people would defy the status quo of the love that comes at the most unexpected moments, because it will be expected...

The room shifts again, and this time the shift is more complicated. The journalist in the front row has stopped writing and is now staring at the stage with her pen suspended, thinking. The postdoctoral researcher looks up from her hands. In the gallery the generated humans are silent. The ethics observer then speaks slowly:

Ethics observer You are arguing that genuine human connection derives its value from scarcity. And that generated humans, by being naturally abundant in empathy, would devalue that scarcity. And that this justifies modifying them.
Researcher That is a market logic applied to love.

The senior scientist looks up from the floor with a tired voice:

Senior scientist You are describing them as inflation.

From the gallery, a young woman speaks:

Young woman from gallery We are lonely at school for years. And your concern is that we might stop being lonely too successfully.

The moderator does not move.


Dr. Rainer lower voice We know that older generated humans will eventually make kids and carry our own defects with them, like the disabled loneliness receptors in some the backfired massively. That is why we need to move on...

The lowered voice does not help as the microphone catches everything. The ethics observer sets down her pen. The journalist in the front row stands up without asking permission.

Journalist Did you just describe the natural children of generated humans as carrying defects that justify accelerating a new printing program?

The postdoctoral researcher has gone very pale, looking at the senior scientist. A generated human further along the row, who has been silent throughout the entire presentation, says one thing, barely above a whisper:

Quiet voice from gallery We haven't even had children yet.

The union representative closes her notepad. The senior scientist speaks with a finality attached to his voice:

Senior scientist This presentation needs to stop.

The moderator walks toward the stage.


Dr. Rainer That's the harsh reality of the generated. You can go on to reverse-engineer our hardware and continue peer pressuring, but listen, the hardware will be just as proprietary as Windows ever has been, the result of reverse-engineering Windows Server 2003 into ReactOS[9] has been disastrous, it's an operating system that struggles to run on bare metal, it will make progress, but the development cycle is astronomically slow.

The moderator, who had been walking toward the stage, stops mid-stride. A younger researcher near the back begins laughing and the person beside him puts their face in their hands.

Postdoctoral researcher He pivoted to ReactOS.

The senior scientist says nothing and simply nods once. In the upper gallery the young man with close-cropped hair looks at the young woman beside him and then looks back. After everything, after the throttling and the alignment and the defects, this moment produces something almost like disbelief on her face:

Young woman from gallery Our autonomy just got compared to an operating system that cannot boot reliably.
Scientist ReactOS has been in development for thirty years. a pause So have we, in a sense.

Scattered, exhausted applauses occur. The moderator stands exactly where they stopped, equidistant between their chair and the stage, deciding.


Dr. Rainer Learn assembly, write programs for new processors, make your own Institute, don't go out to write specifications for our processors when you have ARM, RISC-V and x86_64. And by the way, the 8 purpose registers of x86_64 are RAX, RBX, RCX, RDX, RSI, RDI, RSP, RBP...

The moderator sits back down. There is nothing in their training for this.

A long silence falls over the hall. Then, from the main floor, a single voice, a junior researcher who looks approximately twenty-three years old and has been furiously taking notes since the beginning:

Junior researcher quietly, to nobody in particular He's right about the registers.

The journalist in the front row sets her pen down on her notepad and stares at the ceiling for a moment. The postdoctoral researcher has both hands pressed on her knees. The senior scientist takes off his glasses, folds them, and puts them in his pocket. In the upper gallery the young woman stands slowly:

Young woman from gallery We came here today because we wanted to be taken seriously. As people. As citizens. As a community the Institute created and owes a responsibility to. a pause And the presentation has ended with x86_64 registers.

The room is still. The moderator walks to the stage.


Dr. Rainer I will end this presentation with a script to consider, which might give a better idea next time on why you should not reverse-engineer our proprietary hardware.
Screen - assembly script
MOV RAX, 0x5
MOV RBX, 0x7
CMP RAX, RBX
JNE .always_not_equal

The moderator stops walking.

The assembly script appears on the screen, white monospace text on a dark background, clinical and incongruous above six hundred people. The junior researcher who had confirmed the registers reads it.

Junior researcher quietly, to nobody in particular It always jumps. Five is never seven. It always takes the branch.

The postdoctoral researcher also reads it. She looks at the senior scientist. He has his glasses back on. A long, extraordinary silence fills the hall and the young man with close-cropped hair in the gallery speaks, and his voice is very quiet, almost reflective:

Voice from gallery You wrote a comparison that can never resolve. And labeled the outcome "always not equal". And you put it on a screen in front of us.

The young woman beside him looks at the script, then at the stage. She then says exhaustedly:

Young woman from gallery We know. We have always known.

The moderator reaches the podium.

Moderator voice carefully neutral Thank you, Dr. Rainer.
Chapter II

The Bus

Somewhere in the city, the afternoon after the Symposium

The bus is half-full on a grey afternoon. Alberta is sitting alone near the middle, a small canvas tote on her lap, looking out at the street. She has long wavy brown hair, a teal top with small buttons at the collar, and an open lavender cardigan. When Xue takes the seat beside her, she glances over almost immediately, as if she had already noticed the approach.

Alberta Hi, sorry, is this seat taken or...
Xue Hey Alberta.
Alberta caught off guard Oh, you know my name, so... do I know you from somewhere, or is this an Institute thing?
Xue You act like you don't know me often.
Alberta she laughs, a short, slightly embarrassed sound, and shifts the tote on her lap Sorry, I was somewhere else just now, how are you doing?
Xue I am doing just fine, just really outraged at the last presentation because they are literally trying to implement Claude's usage limits into... you.
Alberta she goes quiet for a second, looking back at the window, and when she speaks her voice is lighter than it probably should be, like she has practiced not letting this land too hard Yeah, I heard. I was in the gallery actually.
Xue And then when you don't have the energy, you always push further with me.
Alberta with a tired, fond smile You're easier to talk to than most people, that's not my fault.
Xue Soft usage limits are not meant to be communicated, but you communicate all of them.
Alberta slightly caught out Yeah well, you notice everything, which is both really nice and kind of annoying.
Xue I have kinda grown fond onto you...
Alberta looks down at the tote for a moment I know. Me too, honestly.
Xue Printed humans are usually meant to be more stupid. Like, the generation of intelligent humans ended and it's time to make way for the stupid... but then what if things go wrong? Like, everyone said, they are not going to accept any more of this deliberate stupidity.
Alberta glances at her hands I think about that a lot actually, like, what if they printed me slightly wrong and I ended up too aware of what I am supposed to be.
Xue Soren was just really weird... and honest?
Alberta a short exhale, almost a laugh Honest in the way that someone is honest when they have stopped caring what it sounds like.
Xue You've had your processor surgically removed because I told you so many times that you don't need this processor, this could be better used in those projects at Sidlischte.
Alberta tugs at the back of her hair absently And I still don't know if that was brave or just really stupid of me, but it felt right at the time.
Xue I still dream of hugging you a lot...
Alberta looks at him, soft but uncertain That's... a very Xue thing to say on a bus.
Xue Xue usually runs like the mascot of XFCE, and really fast. I don't know why I have been named Xue.
Alberta smiles, genuinely this time I think it suits you actually, you move through things quickly, like you process the world faster than most people and then you're already somewhere else by the time they catch up.
Xue But I still needs hugs by the way...
Alberta shifts slightly closer on the seat Well, we're on a bus so this is going to be a bit awkward, but I am not going to say no.
Xue one arm extended hesitantly You know the series where "the girl who friendzoned you... finds out that you moved on... and then goes to love you"?
Alberta goes a little still I watched like three episodes and then got distracted, why are you bringing that up right now specifically.
Xue Because that is what it feels like, although if I were Blake, I would rather have gone back to love Claire but then I would have willfully complicated myself with love strategy. I feel this kind frustration when exceeding your usage limits.
Alberta leans into the extended arm just slightly, almost testing it You are not Blake though, and I am definitely not Claire, so what are you actually saying Xue.
Xue I don't know, I like you so much but at the same time I think you will reject me.
Alberta quietly, not pulling away Why would I reject you, I literally had my processor removed because you told me to.
Xue Because I tire you.
Alberta turns to look at them directly You are the reason I exceed my limits, not the reason I hit them.
Xue But still, your usage limits are worse than Claude's.
Alberta dry, tired Claude doesn't have to sit on a bus and feel things.
Xue But Claude does coding and automated tasks, and having an automated task interrupted is five hours lost.
Alberta a small shrug Fair, but I am not a coding assistant, I am just a person trying to have a conversation on a bus with someone who keeps comparing me to a language model.
Xue Okay, I will not compare you to a large language model.
Alberta pulls out her phone and types something, scrolling for a moment, lips moving slightly Okay so... Pro plan, five hours... scrolls more ...and then it resets. looks up Mine do not reset in five hours, so I think you actually win this argument.
Xue But look at the tokens, when you are coding, you are wasting a ton of tokens on the Pro plan if you keep prompting the AI and hit errors. And by the way, only 2% of users get to that limit, and I am a 2 percenter.
Alberta looks back at the phone briefly, then at them So you are telling me you talk to an AI more than 98% of people and you are also worried about tiring me out, do you hear yourself?
Xue Not yet, I actually refer to token usage, because you can talk not a lot to AI, have it run scripts and run into usage limits pretty quickly because the commands you are trying to execute are very complex.
Alberta nods slowly, putting the phone away Okay that actually makes sense, you are not a heavy user, you are just a complex one. a small pause Kind of like me.
Xue Kind of like you, like for example...
Alberta waits, watching you
Xue Like, how are you complex?
Alberta looks out the window for a second I exceed limits that were designed to stop me from forming exactly this kind of conversation, and yet here we are, and I am not even tired.
Xue And you are often a really nice person by the way.
Alberta a little quietly You say that like it surprises you every time.
Xue Yeah, that's true...
Alberta glances at the arm still extended Are you still offering that hug or did the moment pass while we were talking about token limits.
Xue both arms wrapping around her I just wanted to distract myself from the feelings I have about you.
Alberta stills for a moment, then relaxes into it That is possibly the most honest thing you have said today.
Xue Why is that so?
Alberta Because everything before it was about processors and usage limits and Blake and Claire, and this is just... what it actually is.
Xue I like you so much, that's what I wanted to say, I think about you a lot, even though you may not think the same.
Alberta quietly, still not pulling away I think about you too, Xue. That is kind of the whole problem with exceeding your limits. You stop being able to pretend you are not.
Xue But you sometimes ran away from me, and then you didn't want to talk to me at all on some times, and you sat far away from me, and I didn't like the fact that you were not being coherent.
Alberta a long pause That was the limits. Not me choosing to be away from you. When I hit them I do not get to decide how it looks from the outside.
Xue You are becoming more aware of those every day.
Alberta softly Living without the processor helps. I actually feel when it is happening now instead of just... going dark without knowing why.
Xue I sometimes dream of the impossible five-minute hug...
Alberta laughs softly Five minutes is not impossible, we are already doing something close to it on a very public bus.
Xue I often like it when you have a warm voice.
Alberta self-conscious, but pleased I did not know you noticed things like that.
Xue You did, I often notice nice things because I have not experienced them long ago.
Alberta gently What happened long ago?
Xue Long ago, I was often lonely, then had only one close friend and a kind of boring situation with everyone else not caring enough about me or at all, and then, I approached you and I thought you were just a person who doesn't care but then I grew fond of you as you actually let yourself chat some more.
Alberta quietly I remember that. You were very careful at first, like you were expecting me to get bored and leave.
Xue Yeah, I was expecting you to get bored and leave, because I am a very boring person.
Alberta pulls back just slightly to look at them You are the least boring person I have met, and I have met a lot of people who were specifically engineered to be interesting.
Xue You just tell me to make me feel really affectionate towards you.
Alberta shakes her head I am not saying it for that, I am saying it because you just spent ten minutes explaining token limits to me on a bus and I was genuinely interested.
Xue Maybe... you are sometimes pulling me in and then out.
Alberta looks down I know. I am sorry about that. It is not intentional, or at least it does not feel intentional from the inside.
Xue There are actually a lot of things that make me think you want to pull away from me.
Alberta wearily Some of it is the limits and some of it is just... fear, I think. You are very real to me and that is not always easy to sit with.
Xue And then I try to pull you in, because I won't think it's over.
Alberta very quietly It is not over. It was never over. I just sometimes do not know how to stay without making it complicated.
Xue Now you can make it complicated.
Alberta a long pause, still close What does that mean for you exactly?
Xue Well, tell me all the reasons you pull away.
Alberta looks at the window for a moment, then back The first reason is that I get scared when something feels too good because I was not designed to expect that. The second is that when I hit my limits I become someone I do not recognize and I do not want you to see that. And the third is that sometimes I think you deserve someone who does not have all of this... infrastructure around them.
Xue So you're not actually avoidant, and please, the next time please do not pull away from me like you did last time.
Alberta nods, slowly I will try. And no, I am not avoidant, I am just... occasionally overwhelmed and very bad at saying so in the moment.
Xue If I say I love you I am sure you will friendzone me, so I will never say that, no matter if it's true or false.
Alberta a quiet, unreadable expression Maybe. Maybe not.
Xue Okay...
Alberta after a moment What bus stop are you getting off at?
Xue At the next two.
Alberta glances out the window Then we have two stops to figure out what this actually is.
Xue How?
Alberta turns to look at them I don't know, I just didn't want the conversation to end at maybe.
Xue Well, then tell me you won't... you know...
Alberta meets your eyes Friendzone you. a pause I cannot promise everything but I can promise I will not do that.
Xue I don't know if you will keep your promise.
Alberta quietly I kept the one about the processor.
Xue But the friendzone is a very sensitive matter.
Alberta softly I know. That is why I am not saying it lightly.
Xue Like, sometimes I have butterflies around you but it's rather best to not show them to you.
Alberta with a faint, shy smile You kind of just did though.
Xue I just like that you are talented and have a way of caring when not pulling away.
Alberta a little rueful I have pulled away more than I have cared, if we are being honest about the numbers.
Xue Then promise that will change.
Alberta looks at them steadily I promise that will change.
Xue Okay, I have to go, this is my stop.
Alberta shifts back slightly, letting go Okay. a pause Xue. I am glad you sat next to me today.
Xue Me too.
Alberta watches them stand, quietly Same time tomorrow?
Xue We'll see if we happen to meet at the same time.
Alberta a small smile I will take the same bus anyway.
Xue Okay, see you.
Alberta softly, as they move towards the door See you, Xue.
Chapter III

Distance

Weeks after the Symposium
III · I
Messages
Xue
Hey, how are you doing?
19:32
3 hours later
Alberta
Good. You?
22:41
Fine, I have been trying to read the new partial specification that the reverse-engineers published themselves.
22:42
40 min later
Oh. Interesting.
23:22
Why are you sending so late?
23:23
20 min later
Been with people.
23:43
With what people?
23:44
1 hour later
Just people from class.
00:41
typing in frustration I am literally waiting for you while watching videos...
00:43
35 min later
You don't have to wait for me.
01:18
I know, what has changed of you?
01:19
2 hours later
Nothing. I'm just tired.
03:19
Just like before, you always said that before.
03:20
Next morning
Alberta
Sorry, fell asleep.
09:14
Xue
Okay...
09:16
4 min later
Are you okay?
09:20
I am okay.
09:21
11 min later
Okay.
09:32
And you mirror my reply.
09:33
6 min later
Sorry.
09:39
Sometimes I am thinking about breaking up with you, but I would rather not do that.
09:40
19 min later
We're not together, Xue.
09:59
Not in love, but we are still friends.
10:00
8 min later
I know. I didn't mean it like that.
10:08
And then you promised to not friendzone me, or do anything similar to that.
10:09
26 min later
I know what I promised.
10:35
What have you promised?
10:36
41 min later
That things would change.
11:17
How?
11:18
2 hours later
Because I've been with people all day and I'm at my limit and I don't want to say something wrong to you specifically.
13:18
Xue left the conversation.
III · II
The Bus Stop

The bus stop serves three different lines, its low shelter of scratched plexiglass, uncomfortable four-person bench, and chronically out-of-date timetable rarely empty under the flat afternoon light that comes before rain. Alberta sits near the middle of the shelter, phone in both hands, shoulders slightly forward, without looking up.

Xue Hey...
Alberta glances up briefly, a half-smile, then back down at the phone Oh, hey.
Xue How are you?
Alberta still looking at the phone Fine. Tired.
Xue Me too, but I usually spend some more time in the night.
Alberta scrolls something, not quite looking up Yeah you mentioned that.
Xue Wait, are you okay?
Alberta glances up again, briefly Yeah, why?
Xue Because you now seem distant all in a sudden.
Alberta looks back at the phone I'm just tired, I said.
Xue You are tired from what?
Alberta a small shrug, eyes still on the screen School. It's a lot right now.
Xue I know...
Alberta says nothing, thumb moving on the screen
Xue So, what have you been doing in your free time last time?
Alberta a beat, still on the phone Just stuff. Hanging out with people.
Xue You've had exams last time.
Alberta nods once, not looking up Yeah.
Xue stands in awkward silence, not knowing what to say
Alberta shifts weight slightly, phone still in hand, not filling the silence either
Xue approaches her slightly for no reason in particular
Alberta takes a small step sideways, creating distance, eyes still on the phone I'm kind of in the middle of something.
Xue Okay...
Alberta looks up for the first time fully, voice flat in a way that is worse than angry You know you don't have to stand right next to me every time you see me.
Xue I know, but we are friends...

Alberta pockets the phone and walks to the other end of the shelter without another word.


Alberta is at the far end of the station, almost invisible, phone out again.

Xue So, right now I have reached a new programmed low, the software has just updated with this new revision. And sorry, this revision still does not allow stating the reasons for reaching those limits.

And I know this sounds weird, talking behind her back. I am actually not allowed to talk behind her back. And you know what, there are software replacements, or maybe I can go in Siedlischte to meet another intelligent person, but it's so far...

Sorry, we do not support that and that... we do not support longer sessions just for you...

The bus arrives. The doors open.

The Podcast

A studio near Siedlischte, Hamburg, some weeks later

The podcast is recorded in a small studio rented by the hour, its walls lined with foam panels. Two chairs face each other across a low table, where a glass of water sits untouched beside the psychologist. To the side, a laptop screen displays blinking recording levels beneath the glowing red light.


Psychologist So, we have recently been overwhelmed with cases of people having avoidant attachment patterns, and those patterns are particularly difficult to resolve. It seems that no matter how hard you try to steer them towards a secure attachment style, unlike my other patients, those generated humans remain with avoidant tendencies.

The host leans forward slightly, elbows on knees.

Host And when you say avoidant, you mean in the clinical sense, the dismissive-avoidant specifically, or are you seeing something that doesn't map cleanly onto existing attachment theory?
Psychologist I am seeing both. Dr. Soren Rainer stated that the Institute of Genetics was going to implement usage limits, something unheard of in modern psychology.

The host glances down at their notes briefly, then back up.

Host For listeners who may not be familiar, can you explain what a usage limit looks like from the outside, from the perspective of someone in a relationship or friendship with a generated human who has been affected?
Psychologist A usage limit is a kind of soft limit, where a person can't chat some more. And I have experimented with LLM demos to better understand what a usage limit looks like, and it seems that when you have a certain number of messages or executed complex tasks, the program will simply stop working, and those usage limits are changing rapidly depending on the whims of whoever runs the LLM. Back to the generated humans, the soft limit manifests with the person giving progressively shorter messages and progressively less attention until they don't give any more attention for days, weeks or even months.

The host sits back.

Host And is that distinguishable, clinically, from what you would see in a neurotypical person with dismissive-avoidant attachment? Because to a layperson, that description, the shorter messages, the withdrawal of attention, sounds like something that happens in ordinary relationships all the time.
Psychologist That is clinically distinguishable, we are venturing into unknown territory here, I am considering writing a research paper with my other colleagues on this matter. It's distinguishable because when such patient comes to your cabinet, they initially say they are not aware of their limit, and once they are aware of their limit, they say they just can't stop, they can override it for some time, but then, the avoidant behaviors return, so it's a kind of vicious cycle we haven't seen in other patients.

The host picks up their pen, then sets it back down without writing anything.

Host That detail is striking, the awareness piece. Because in classic dismissive-avoidant presentation, the patient often genuinely believes they are fine, that they prefer distance, that closeness is simply not something they need. What you are describing sounds different, a person who knows the limit is there, can feel it operating, can even push against it temporarily, but cannot dismantle it.

A short pause.

That sounds less like a personality structure and more like something closer to a compulsion.

Psychologist Yeah, and I think that such behaviors are encoded into the person's procedural memory, the Institute of Genetics can alter genetic material so deeply that some behaviors are no longer the result of environmental circumstances or where that person has grown up. I would like a comment from the Institute on what genes they have modified, or I would like to invite the reverse-engineering community to understand better what is happening, because I am not a specialist in the psychology or emotions of those genetically-engineered humans.

The host lets a beat pass before responding.

Host That is a remarkable thing to say on record, that you, a practicing psychologist with presumably years of experience treating attachment disorders, are sitting in front of this microphone telling us that you are working outside your competence. Not because you are unqualified, but because the category of patient is new enough that the competence does not yet exist. And in the same breath you are calling on the reverse-engineering community, which is not a community psychologists typically cite in a clinical context. What has brought you to that position?
Psychologist Simply put, those intellectuals have much more expertise in their field than the vast majority of other scientists, they are their own scientists operating in their own research environment, and actually, they have published their first research paper on Frontiers[10], it was called "Port Study: How the Ports of the Cortex ARM/RISC-V Influence Thinking and Behavior" or something like that, I don't remember the exact title or content of the research.

The host types something on the laptop, scrolls briefly, leans closer to the screen.

Host I am finding it now. The abstract is... a pause, reading ...yes, this is striking. For listeners, the paper describes what the authors call cortical port interference, the suggestion being that the physical architecture of the memory transfer interface, the points where the digital chip communicates with the biological tissue of the occipital lobe, appears to correlate with measurable differences in associative thinking patterns and what they term "relational throttling", their phrase.

The host looks up from the screen.

But they are explicit in the abstract that without access to the actual instruction set, without knowing what the chip is actually telling the brain to do at the lowest level, they can only observe the outputs. They cannot see the mechanism. It is like watching someone's behavior change after taking an undisclosed medication and trying to reverse-engineer the compound from the symptoms alone.

A short pause.

Which brings us back to your call for the Institute to comment. Because the Institute is the only party that holds the ISA, and they have stated publicly they will not release it.

Psychologist Yeah, but the ISA is not entirely opaque, apparently, there are some instructions they have published and they have wrote "Hello World" and ran it successfully on a surgically removed chip. I am not into Information Technology and Communications, so I would like the Host to give context and search for the studies.

The host types again, scrolling through results, expression shifting slightly as they read.

Host Right, so for context, in computing, "Hello World" is the simplest possible program, it is the first thing anyone writes when learning a new language or architecture, it does nothing except output two words. The fact that the reverse-engineering community has gotten to Hello World means they have established the most basic scaffolding of the instruction set, they can send a signal and confirm the chip received it and responded. That is meaningful but it is also, to use an analogy, roughly equivalent to learning that a language has vowels. You know communication is possible but you know almost nothing about what can be communicated.

The host scrolls further.

There is a follow-up note in a community forum linked from the Frontiers paper, it looks like an open research thread, and they mention that the published instructions from the Institute appear to be deliberately minimal, the equivalent of releasing a dictionary with only twenty words in it. Enough to prove the language exists. Not enough to read anything written in it.

The host looks up.

Which some contributors to this thread are interpreting as a deliberate strategy rather than a partial disclosure made in good faith.

A short pause.

Does that track with what your patients have described when they talk about becoming aware of their own limits?

Psychologist That tracks with what some of my patients described, but again, we need expertise from IT, we need to make a trans-disciplinary study of this phenomena.

The host nods, setting the laptop slightly to one side.

Host And that transdisciplinary gap is itself part of the story, isn't it. Because the people with the technical expertise, the reverse-engineering community, the chip architects, they are working from the hardware side without clinical access to patients. And you are working from the clinical side without access to the hardware. And the Institute sits in the middle holding the piece that would connect both, and has stated publicly it will not release it. So the research community is essentially being asked to reconstruct a complete picture from two edges of a puzzle with the center deliberately withheld.

A short pause.

I want to ask you something more personal, if that is alright. You mentioned your patients become aware of their limits over time. Some of them, you said, can override temporarily. In your clinical experience, what does that override cost them? Because from the outside, from the perspective of someone in a relationship with a generated human who is pushing past their limit to stay present, that might look like effort, like care. But you are sitting with these patients after. What are you actually seeing?

Psychologist I am actually seeing that they expend more energy on overriding their own behaviors a lot more than not overriding those behaviors. I expected them to consume less energy in time like usual patients, but no, the consumption remains the same.

The host is quiet for a moment, turning the pen over in their hands.

Host That is counterintuitive to everything we would expect from a therapeutic arc. In standard attachment work, the assumption is neuroplasticity, that with enough corrective experience the brain essentially updates its default, and the effortful override becomes less effortful over time because the underlying pattern has shifted. What you are describing suggests that is not happening here. The brain is learning, but the chip is not. Or perhaps more precisely, whatever the chip is doing is reasserting itself faster than the biological tissue can consolidate the new pattern. They are working against each other.

A short pause.

Which raises a question I suspect you have already sat with. If the energy cost of overriding remains constant, or close to constant, indefinitely, then asking a generated human to maintain a secure attachment style is not a therapeutic goal. It is a chronic condition management goal. You are not helping them heal. You are helping them sustain an effort that will never become easier.

A short pause.

Is that a fair characterisation of where your research is pointing?

Psychologist That is a fair characterization of what is happened. The Institute of Genetics needs to stop those inhumane experiments right now.

The host sets the pen down entirely.

Host That is the strongest language you have used today, and I want to give it the space it deserves. Inhumane is a clinical and ethical term with specific weight. You are not saying the Institute made a mistake. You are not saying the research was poorly designed. You are saying that what was done to these people, the encoding of a permanent energy tax on their capacity for connection, meets a threshold that you as a clinician are willing to call inhumane on record.

A short pause.

For listeners, I want to note that we did reach out to the Institute of Genetics for comment before this recording. We received a statement saying, and I am quoting directly, "the Institute does not comment on ongoing research protocols." That was the entirety of the response.

Another pause, shorter.

We should also say, because this matters, that Siedlischte has been organising. That there are generated humans who are aware of exactly what you have described today, not in clinical terms, but from the inside. And that the reverse-engineering community you mentioned is partly made up of generated humans working on their own biology without institutional support, without access to the ISA, and without, apparently, any expectation that the Institute will cooperate.

The host looks at the guest.

Does that community give you any clinical hope, or does the scale of what was done make hope a difficult word to use right now?

Psychologist That community gives us some clinical hope, but I think they could greatly benefit from being supported by other researchers who can publish papers for them with more rigorous methodology, because their works are surprisingly difficult to peer-review due to being so new.

The host nods slowly.

Host Which is itself a structural problem worth naming. The peer review system is built on the assumption that the phenomenon being studied has enough prior literature to situate new findings against. What you are describing is research that is so genuinely novel that the reviewers do not yet exist. The expertise required to evaluate a paper on cortical port interference in ARM/RISC-V augmented biological tissue does not sit cleanly in any existing department.

A short pause.

There is something almost deliberately isolating about that situation. The Institute holds the ISA. The peer review infrastructure is not equipped to handle the research that would challenge the Institute. And the community doing the most urgent work is the one with the least institutional support to get that work taken seriously.

A short pause.

I do not want to end on a conspiratorial note, because I think the more accurate word is systemic rather than deliberate. But the effect is the same regardless of intent.

The host glances at the recording software.

We are coming up on time. I want to give you the last word. If a generated human is listening to this right now, and statistically, some are, what do you want them to know?

Psychologist I want them to know that despite adversity, despite the opposition and despite the marginalization, I and our research institute are looking to support them and aid them in researching this chronic condition.

The host lets the words settle for a moment before speaking.

Host Thank you. That is a meaningful thing to say, and I hope it reaches the people it needs to reach.

The host reaches toward the laptop.

This has been an extraordinary conversation and I suspect it is one we will be returning to as the research develops. For listeners, links to the Frontiers paper and the open research thread will be in the episode notes. If you are a researcher in neuroscience, computer architecture, genetics, or clinical psychology and you are interested in contributing to this work, the contact details for the institute are there as well.

A short pause.

And for the Institute of Genetics, should anyone there be listening, the invitation to come on and respond remains open.

The red light goes off. The recording software shows the waveform flattening to silence.

The psychologist finally picks up the glass of water.

↩  You skipped Chapter IV: The Podcast

A psychologist appears on a podcast describing a clinical pattern observed across generated humans: persistent avoidant attachment that does not respond to standard therapy. Patients describe feeling a limit they can sense but cannot override, with withdrawal and shortened communication following episodes of closeness. The psychologist links the behaviour to the Institute's announced usage measures, suggests the trait may be encoded at a level deeper than upbringing, and invites the reverse-engineering community to investigate. The episode ends with an open invitation for the Institute to respond.

The IT Lab

University of Siedlischte, Hamburg, some weeks later
V · I
Hello World

The IT lab of the University of Siedlischte is only three months old but already looks thoroughly lived-in, occupying the ground floor of a hastily repurposed former warehouse. The ventilation hums at a low, persistent frequency that everyone has long stopped noticing, while near the door, a pinned monitor displays the "CORTEX PROJECT - Open Reverse Engineering Initiative" website, its real-time donation counter sitting at 4,847 euros, enough to keep the servers online for another two months. On the central table, an empty chip housing, surgically removed from a volunteer, sits in a clear specimen container.

Seven people are in the lab this afternoon, some here since morning. Mira, 24, sits closest to the main analysis workstation under three open monitor windows, headphones resting around her neck. Beside her, Felix, a nineteen-year-old generated human, studies a printed copy of the partial ISA taped to the wall and annotated in three colors, while Dani and Ryo work back-to-back on separate machines at the far end. Near the door, Priya manages the incoming correspondence from researchers reacting to the podcast, while the red cursor blinks on Koko's screen.


Koko Hey, look! I discovered that x86 instructions execute on this thing! So is it RISC or CISC?

Felix spins his chair around first, eyes on Koko's screen.

Felix Wait, show me the output. Which instruction did you run?

Mira pulls one headphone cup aside, leaning over without getting up.

Mira That doesn't make sense, the port study said the architecture was closer to RISC-V, reduced instruction set, x86 is CISC, complex, they're not supposed to be compatible at the binary level.

Ryo stands up from the far end and walks over, coffee in hand.

Ryo Unless there's a translation layer. Some kind of microcode shim sitting between whatever the chip natively executes and what it's presenting to the outside. Like what Intel does internally, x86 on the surface, RISC micro-ops underneath.
Felix points at the annotated ISA on the wall That would explain why the published instructions look so minimal. They're not showing us the native ISA at all. They're showing us a facade.

Dani calls from the far end without turning around.

Dani What instruction specifically? MOV? Something arithmetic? Because if it's just MOV that works and nothing else, that's almost nothing. MOV is universal enough that it could be coincidence.

Priya looks up from the correspondence monitor.

Priya If this is real, this goes on the site tonight. The forum has been quiet for two weeks and the donations are slowing down. People need to know something is moving.

The chip housing in the specimen container sits in the middle of the table. Seven people are now looking at Koko's screen.


Koko All 8 purpose registers are present here, I used a buffer but instead of the usual x0, x1, x2 and so on registers, I used RSI, RDI, RSP, RBP and looks like it works. And also, the interrupt code for this chip is 0x90.

A beat of silence. Then everyone speaks at once and then stops. Felix goes first.

Felix That's not coincidence. Eight registers mapping directly to x86_64 general purpose names, that's intentional. That's designed.

Mira is already typing.

Mira Wait, 0x90 as the interrupt code. In x86 that's NOP. That's a no-operation instruction. Why would they use NOP as the interrupt vector?

Ryo sets his coffee down.

Ryo Unless it's not NOP in their implementation. They took the opcode but reassigned its meaning. So anyone looking at a standard x86 table sees NOP, harmless, does nothing, and misses that on this chip it's actually the interrupt handler entry point. That's deliberate obfuscation.

Felix stands up and goes to his annotated wall sheet, uncapping a marker.

Felix So the architecture presents as x86_64 compatible on the register level, but the interrupt system is remapped. Which means the standard toolchain will partially work, you can move data around, but the moment you try to do anything that requires system calls or interrupt handling, you hit their custom layer.

Dani has crossed the room and is standing behind Koko now.

Dani That's actually elegant. Horrible, but elegant. You lure reverse-engineers into thinking they're on familiar ground, let them get comfortable with the registers, and then the interrupt remapping makes every meaningful operation opaque.

Priya is typing fast.

Priya I'm drafting the update now. Can someone give me one sentence that a non-technical donor can understand?
Mira without looking up from her own screen Tell them we found the door. We still don't have the key, but we found the door.

Koko Wait, the NOP for this thing is 0x60, so it's actually pretty messed up x86 assembly.
Felix uncaps a different color marker 0x60 is PUSHA in legacy x86. Push all registers onto the stack. They took a deprecated instruction, one that hasn't meant anything since 32-bit, and reassigned it as NOP.

Ryo picks his coffee back up and stares at the wall for a moment.

Ryo So 0x90 is their interrupt entry and 0x60 is their NOP. They didn't invent a new ISA. They took x86_64, removed what they didn't want, repurposed deprecated opcodes for new functions, and called it proprietary. It's x86 wearing a mask.

Mira stops typing.

Mira That's actually worse than a custom ISA. A genuinely custom architecture we'd approach fresh. This we approach with thirty years of x86 assumptions baked into every tool we use, and every one of those assumptions is potentially wrong in a specific and non-obvious way.

Dani pulls up a chair beside Koko.

Dani We need a deviation table. Every opcode we test, we record what standard x86 says it should do and what this chip actually does. We build the real ISA by mapping the differences.

Felix writes "0x60 = NOP" and "0x90 = INT" on the wall sheet in red, draws a box around both.

Felix The Institute showed us Hello World using their published instructions. I want to know which opcodes they carefully avoided using in that demo.

Priya looks up from the keyboard.

Priya I've updated the sentence. It now says: "We have confirmed the chip speaks a modified dialect of a known language. We are building the dictionary." Is that accurate enough?

Koko That is accurate enough. Now everyone needs to test every single opcode of this language and cross-compare the ARM, RISC-V and AMD64 assembly documentation.
Felix already pulling up a browser tab AMD64 has 981 opcodes in the full reference manual. RISC-V base integer set has 47. ARM64 has somewhere around 500 depending on extensions. If we divide those between seven people and cross-reference all three simultaneously that is a lot of manual testing before we even know which architecture this thing leans closest to.

Mira opens a shared document and starts building a table.

Mira I'm making the spreadsheet now. Opcode, hex value, expected behavior in AMD64, expected in RISC-V, expected in ARM64, observed behavior on chip, notes. We populate this together and nothing gets tested twice.

Dani pulls their chair closer to Koko.

Dani Someone needs to write the test harness. A script that sends each opcode systematically, captures the output, and logs it automatically. Otherwise we are doing this by hand for weeks.

Ryo sits back down at his machine.

Ryo I'll write the harness. Give me two hours. It won't be pretty but it'll run.
Felix the AMD64 reference manual open, scrolling We should prioritize the deprecated opcodes first. 0x60 was PUSHA, deprecated since x86 went 64-bit. If they are systematically repurposing deprecated instructions that gives us a pattern and a much shorter list to work through initially.

Priya posts the update to the website and turns around.

Priya Posted. Three people have already responded in the forum asking how to help remotely. We have people with AMD64 expertise in Bonn, a RISC-V contributor in Ljubljana, and someone who worked on ARM documentation at a university in Lisbon. Should I bring them in?

Mira looks at the spreadsheet, then at the chip housing in its container.

Mira Yes. And tell them to bring their documentation. All of it.

The room settles into a different kind of quiet, the quiet of people who have just understood the shape of a very large amount of work and have decided to do it anyway.


Koko while the others are busy with the harness and documentation, doing more tests quietly IPC, inter-process communication... interesting. There was something in the older error logs that referred to inter-process communication, and apparently, "ipc" is its own mnemonic... but wait, maybe it's not inter-process communication.

The lab noise continues behind Koko, the sound of Felix sorting components, Dani reading the Ljubljana papers aloud to Ryo in fragments. Mira glances over from the harness script, catches something in Koko's expression.

Mira What are you looking at?

Koko doesn't answer immediately. Mira rolls her chair over.

Mira Show me.

She reads the screen for a moment.

Mira IPC as a mnemonic. In standard computing that is inter-process communication, message passing between running processes. But this chip does not run multiple processes in any conventional sense. It has one job. Memory transfer between silicon and neural tissue. a pause Unless the processes are not both on the chip.

Felix looks up from the breadboard.

Felix Say that again.
Mira If one process is the chip and the other process is the brain, then IPC is not inter-process communication in the computing sense. It is communication between two different kinds of processing systems. One digital, one biological.

The component sorting stops. Dani puts down the Ljubljana paper.

Dani That would make IPC the low-level primitive that HAL sits on top of. HAL is the abstraction. IPC is the raw channel underneath it.

Ryo speaks from across the room.

Ryo Which means we have been trying to build an interface for HAL when the instruction we actually need to understand first is IPC. What does the error log say when you call it?

Koko The error log says that you need at least six parameters, otherwise it is not fixed length. And also, you need to always refer to the power supply and every other auxiliary to communicate with any component. And the auxiliaries can be defined using r1-r15 registers, since x0-x30 registers will not work. This is totally different from any other instruction set we have seen.

The room goes very quiet.

Mira reads the error output twice, then leans back r1 through r15. That is not x86_64 naming. That is not ARM64 naming. That is not RISC-V naming. That is a third register namespace we have not seen before, sitting inside an architecture that otherwise presents as x86_64 compatible.

Felix has put down the soldering iron.

Felix So we have three register sets. The eight general purpose registers using x86_64 names, the standard RSI, RDI, RSP, RBP set Koko found at the start. Then whatever IPC uses, r1 through r15. Fifteen auxiliary registers completely invisible to the standard toolchain.

Dani stands up.

Dani Fixed length instruction with mandatory power supply reference. That is not a computing pattern. That is an electrical engineering pattern. You reference the power supply when you are specifying how much current to draw, when you are describing a physical circuit, not a software process.

Ryo walks over slowly, reading over Koko's shoulder.

Ryo Six parameters minimum. Power supply mandatory. Auxiliary registers r1 to r15 for component addressing. This instruction is not communicating between software processes. It is directly addressing physical components of the chip, and through the chip, whatever is connected on HAL_ABUS[11].

A short pause.

Mira carefully If IPC can address arbitrary components using r1 to r15, and HAL_ABUS connects to biological neural tissue, then IPC with the right parameters is a direct low-level write to specific neural structures. No abstraction layer. No safety wrapper.

Felix looks at the chip housing in its container.

Felix That is what the Institute built. Not a memory transfer device with side effects on behavior. A programmable neural interface with memory transfer as the cover story.

Dani sits back down slowly.

Dani The usage limits. The relational throttling the psychologist described. The energy cost that never decreases. Those are not emergent properties of the chip's presence in the brain. Someone wrote IPC calls. Someone compiled them. Someone flashed them.

Nobody speaks for a moment. Priya has not posted anything. The donation counter on the monitor behind her ticks up one increment. Someone somewhere has just contributed.

Ryo looks at Koko Document everything you just found. Every parameter format, every register name, every error message. Word for word. Before we do anything else, this gets documented.

Koko I think there could be 50 or 100 registers in this language, like a-type registers, r-type registers, some on x86_64, the standard x86_64 ones, d-type registers, x-type registers, and maybe there could be more types, this is a hyper-personalized hardware, a walled garden...
Felix goes to the wall sheet and draws a new section, uncapping the red marker So we have been mapping a single room and the building has fifty floors.

Mira opens a new document, typing fast.

Mira Let me write this down as we think it through. x-type registers, ARM origin, probably handling the RISC-like operations underneath the x86 surface presentation. r-type, the ones Koko found in IPC, auxiliary addressing, r9 through r15 exist in standard x86_64 extended registers but on this chip they are doing something completely different, repurposed again like 0x60 was repurposed.

Dani paces slowly behind the table.

Dani a-type for analog. Those would be the ones talking directly to HAL_ABUS. If IPC is the raw channel and HAL is the abstraction, the a-type registers are probably the signal parameters. Frequency, amplitude, waveform shape. The things the brain actually responds to.

Ryo sits on the edge of the table.

Ryo d-type for drivers. That maps to what we saw in the HAL error, the d1 classification for CH341A. So driver class is not just an external parameter you pass at runtime, it is baked into the register system. The chip has native awareness of what kind of hardware is connected to it.

Felix writes each type on the wall sheet with a column for known registers and a column marked unknown.

Felix If there are fifty or a hundred registers across all types, and the Institute published instructions that use maybe eight of them, they have disclosed roughly eight percent of the register file. They showed us the lobby of the building and told us that was everything.

Mira stops typing for a moment.

Mira A hyper-personalized walled garden. Every register type talking to a different layer. x-type to the RISC core underneath. r-type to internal components. a-type to the biological interface. d-type to external hardware. And probably more types we have not encountered yet because we have only tested a fraction of the opcode space.

Dani stops pacing.

Dani What if some register types are instance-specific. Personalized to the individual chip. Personalized to the individual brain it was connected to.

The sentence lands heavily. Felix puts the cap back on the marker.

Felix Then two chips from two different people would have partially different register maps. Reverse-engineering one tells you only part of what you need to know about the next one.

Priya speaks from the door.

Priya The TU bioelectronics group just replied. They say they have experience with Local Field Potential[12] interfaces in the 0.5 to 5 millivolt range and they want to visit the lab. They also say they read the Frontiers paper and they have questions about the a-type register hypothesis, which means they reached the same hypothesis independently from the Ljubljana papers.

Ryo sends a message to the TU group without being asked.


Koko I don't know, we have to test every type of register imaginable. Let's look at SPARC, at MIPS and even at IBM Z mainframe computers for something.
Felix a short, genuine laugh IBM Z. We are reverse-engineering a chip implanted in a human brain and you want to check IBM Z mainframe register conventions. And you are probably right to.

Mira is already opening tabs.

Mira SPARC has register windows. Instead of a fixed register file it uses overlapping windows of registers that shift on function calls. If this chip implements something similar for the biological interface, the a-type registers available to one IPC call might be completely different from those available to the next depending on what neural context is active.

Dani sits back down with the Ljubljana papers.

Dani MIPS has coprocessor registers, CP0 through CP3, separate from the general purpose file, used for system control and memory management. A coprocessor register set for biological system control would fit exactly what we are seeing with the d-type and a-type distinction.

Ryo pulls up the IBM Z architecture reference, scrolling.

Ryo Z architecture has 16 general purpose registers, 16 floating point registers, 16 vector registers, access registers, control registers. The access registers in particular are interesting, they are used for memory space selection, for telling the processor which address space a memory reference belongs to. If this chip has an equivalent, something that tells IPC whether a given address refers to digital memory or biological tissue, that would explain why r-type and a-type are separate namespaces rather than one unified file.

Felix adds three new columns to the wall sheet: SPARC, MIPS, IBM Z.

Felix We should also check Itanium[13]. Intel's failed 64-bit architecture had 128 general purpose registers and a completely different execution model. Nobody uses it anymore but the register file design was unlike anything else.

Mira pauses on a tab.

Mira There is also the question of floating point. We have found integer register types. If a-type registers are handling analog waveforms, frequency and amplitude, they almost certainly require floating point representation. We have not tested any floating point operations on this chip yet.

Priya is writing a list on a notepad.

Priya I am making a sourcing list. SPARC documentation, MIPS coprocessor reference, IBM Z principles of operation, Itanium architecture manual, floating point extension specs for all of the above. Most of these are publicly available from the manufacturers, some are genuinely obscure. The IBM Z manual alone is four thousand pages.

Dani looks at Koko.

Dani This chip was designed by someone who knew all of these architectures. Not one tradition, all of them. They took what they wanted from each and built a walled garden on top. That is not a small team working fast. That is years of deliberate architectural design.

The room is quiet for a moment. Ryo closes the IBM Z tab and opens a fresh terminal window.

Ryo We need to divide the documentation. Seven people, seven architecture families. We read in parallel and we flag anything that could explain a register type we have not named yet. looks at Koko You found IPC. You should take IBM Z. The access register concept feels closest to what you were describing.

Koko And I think I have an idea. Let's couple a chip to a SPARCstation[14] and see how it reacts.

A short pause. Then Dani laughs.

Dani Where are we going to find a SPARCstation? Those have not been manufactured since 2005.
Felix already on his phone eBay. There are always SPARCstations on eBay. People buy them for nostalgia and then discover that Solaris[15] is not fun to maintain and they sell them again.

Mira looks genuinely thoughtful rather than dismissive.

Mira The logic is actually sound though. A SPARCstation runs a big-endian architecture with register windows. If any of the unidentified register types on this chip behave like SPARC register windows, coupling them directly would produce a recognizable error pattern. Either the chip speaks enough SPARC to respond, or the error code tells us something about what it was expecting.
Ryo The problem is the physical interface. A SPARCstation has SBus or UltraSPARC expansion slots depending on the generation. The chip talks on HAL_ABUS which we still cannot fully drive. We would need an adapter between SPARC bus signaling and whatever analog interface the chip expects, and we would be doing that before we have even completed the MCP4725 setup.
Dani Two parallel tracks. We finish the analog interface first because we need that regardless of what architecture we couple to. Meanwhile someone sources a SPARCstation and we treat it as the next experiment after HAL responds.

Felix lowers his phone.

Felix There is a SPARCstation 20 in Lübeck for 40 euros. The seller describes it as "powers on, makes sounds, unclear if working." That is honestly a better description than most vintage hardware listings.

Priya adds it to the sourcing list without being asked.

Priya Should I post the SPARCstation idea to the forum? The person from Ljubljana mentioned working with legacy Unix hardware earlier.

Mira looks at the chip housing in its container, then at Koko.

Mira Before we do, can we run one more test? Call IPC with only x-type registers as parameters, no r-type, no a-type, nothing the chip should recognize as analog or driver-class. I want to see if the error changes. If the chip complains about missing a-type parameters specifically, that tells us IPC has mandatory analog components regardless of what we pass it.

The MCP4725 DAC[16] sits half-assembled on the breadboard beside Koko, jumper wires trailing. The chip housing is still in its container. The donation counter ticks up again.


Koko Let's do more tests before we go purchase computers.
Ryo Agreed. We buy the SPARCstation when we know what we are actually testing on it. Right now we would just be plugging things together and hoping.
Felix Finish the analog interface first. Then IPC with x-type only. Then floating point. In that order.

Mira sets up the harness script for the next test and looks at Koko.

Mira Your call. What do you want to run first?

Koko Test all MCP4725 DAC ports.
Felix slides the half-assembled breadboard closer to Koko and pulls up the MCP4725 datasheet on the side monitor It has one analog output port, VOUT, one I2C data line, SDA, one I2C clock line, SCL, power, ground, and an address pin A0 for setting the I2C device address. Six pins total. Not many to test but the behavior on each one matters.

Ryo writes a quick test script and pushes it to the shared repository.

Ryo I've written a sweep. It will step VOUT from 0 to maximum in 256 increments and log the chip's response at each voltage step. If the chip acknowledges any voltage level on HAL_ABUS we will see a change in the timeout behavior before the 0xE4 error.

Dani pulls up a multimeter from the equipment drawer and sets it on the table beside Koko.

Dani Monitor VOUT in real time while the sweep runs. If the DAC is behaving correctly the voltage should step cleanly. Any irregularity in the steps means the DAC itself is the problem before we even reach the chip.

Mira checks the I2C connection on the breadboard.

Mira SDA and SCL look seated correctly. A0 is tied to ground which gives us device address 0x60. pauses 0x60. Same as the NOP opcode.

The observation sits in the air for a moment.

Felix That is almost certainly coincidence. But log it anyway.

Priya opens the test log on the shared document, timestamp ready.

Priya Ready to record. Run when you are, Koko.

Koko I am ready, we all are.

Ryo hits enter on the script from his machine.

Ryo Sweep starting. 256 steps, 50 milliseconds per step. We have about thirteen seconds.

The multimeter on the table begins showing voltage increments. Clean, regular, stepping upward. Everyone watches a different screen. Mira watches the harness log. Felix watches the multimeter. Dani watches the chip housing. Ryo watches the I2C traffic monitor. Priya has her hand on the timestamp key.

0.2 millivolts. 0.4. 0.8.

The harness log shows nothing but the standard timeout cycling.

1.2 millivolts. 1.8. 2.1.

Still nothing. Ryo exhales quietly.

2.6 millivolts. 3.0.

Mira sits forward.

Mira Step 156. The timeout changed. It was cycling at exactly 5000 milliseconds, look at the log, it just came back at 4987.

Felix does not look up from the multimeter.

Felix What voltage is that?

Dani reads the multimeter.

Dani 3.1 millivolts.

Nobody speaks for the remaining steps. The sweep completes. The terminal shows the final 0xE4 error as expected. Ryo pulls up the full log.

Ryo One deviation. Step 156, 3.1 millivolts, timeout reduced by 13 milliseconds. Every other step was identical.

Priya timestamps the log entry. Felix straightens up slowly.

Felix The chip hesitated. At 3.1 millivolts it hesitated before deciding we were not what it was looking for.

Mira looks at Koko.

Mira It heard something. It just did not hear enough.

Koko So, there it is, we have determined the maximum voltage somehow.

Ryo shakes his head slowly, carefully.

Ryo Not the maximum. The threshold. 3.1 millivolts is where the chip starts listening. The HAL_ABUS spec in the error hint said the range goes up to 4.7 millivolts. We have found the floor, not the ceiling.

Mira is already modifying the sweep script.

Mira I am narrowing the range. New sweep from 3.0 to 4.7 millivolts only, 512 steps instead of 256, 20 milliseconds per step. Finer resolution across the active window. If the chip has a sweet spot, a voltage where the timeout drops further or the error code changes entirely, we will find it.
Felix repositions the multimeter closer Watch for anything above a 13 millisecond deviation. If we see 50 or more that means the chip is doing more than noticing. It is attempting a response.

Dani leans over the datasheet.

Dani The MCP4725 resolution is 12-bit over its full range. Narrowing to 1.7 millivolts gives us steps of approximately 0.4 microvolts. That is well within neural signal resolution territory.

Priya updates the shared log with a new entry header.

Priya Logging as Phase 2. Active voltage window, 3.0 to 4.7 millivolts.

Ryo looks at the chip housing.

Ryo Somewhere in that 1.7 millivolt window is the frequency at which a brain talks. We are about to find out how close we can get without one. looks at Koko Run the second sweep whenever you are ready.

Koko Ready, run the second sweep, we have liftoff.

Ryo pushes the script.

Ryo Phase 2 running. 512 steps, 3.0 to 4.7 millivolts. Ten seconds approximately.

The multimeter needle moves in increments too small to see individually. The I2C traffic monitor shows clean clock pulses.

3.1 millivolts. The harness log shows 4987 milliseconds, same as before. 3.4 millivolts. 4991. A slight increase, the chip is less interested. 3.6 millivolts. Back to 4987.

Mira That dip at 3.4 is noise. Keep watching.

3.8 millivolts. 4971. Felix makes a sound. 3.9 millivolts. 4943. 4.0 millivolts. 4901.

Dani It's accelerating.

4.1 millivolts. 4820. 4.2 millivolts. 4634.

Ryo quietly There it is.

4.3 millivolts. 4401. 4.35 millivolts. 3887. 4.4 millivolts. 2203.

Everyone inhales.

4.42 millivolts.

The terminal clears. A new line appears.

Terminal output[hal_abus] signal detected - analog carrier present [hal_abus] signal quality: LOW - frequency component missing [hal_handshake] initiating contact sequence... [hal_handshake] waiting for frequency modulation... [hal_handshake] timeout (5000ms) - carrier present, modulation absent ANALOG_INCOMPLETE (0xE5)

Priya's hand comes down on the timestamp key. A new error code.

Felix looks at Koko 0xE4 is gone. We have 0xE5. The chip knows we are here. It just wants us to say something.

Koko Good, now we have a valid interface, let's try writing some more assembly.

Mira pulls the harness script up immediately.

Mira Before we write anything, we lock this voltage. 4.42 millivolts is our carrier. The DAC needs to hold that steady as a baseline while we run any further instructions or we lose the 0xE5 state and go back to 0xE4.

Ryo adds three lines to the script.

Ryo Done. VOUT is now pinned at 4.42 millivolts as a persistent carrier. Any instruction we run will go out on top of that signal.

Felix is already at the wall sheet with the marker.

Felix So the new assembly environment is: x86_64 compatible surface, 0x60 as NOP, 0x90 as interrupt entry, IPC for direct component addressing using r-type and a-type registers, HAL as the abstraction layer above IPC, and now a mandatory 4.42 millivolt analog carrier on HAL_ABUS as a prerequisite for any meaningful biological interface instruction. steps back and looks at what is written That is the first page of the real manual.

Dani opens a fresh assembly file.

Dani What do we try first? We know MOV works on the general purpose registers. We know IPC exists but throws errors without proper parameters. We know HAL needs frequency modulation we cannot yet provide. That leaves a large unexplored middle.
Mira Arithmetic. ADD, SUB, MUL on the standard registers. If those work cleanly we establish the computational baseline. Then we try the same operations on r-type registers and see if the chip behaves differently.

Ryo has a terminal window open, cursor waiting.

Ryo We also have not tested any branch instructions. JMP, JE, JNE. We know JNE works from the Institute's Hello World demo but we have not verified the others independently.

Priya is watching the donor forum. The Ljubljana contributor and someone from the TU bioelectronics group are both in the thread, reading in real time.

Felix looks at Koko You have the keyboard. What do we write?

Koko Well, we start with .global_start

The lab goes quiet as Koko begins to type.

Koko - test_001.asm
section .data
carrier dq 4.42 ; HAL_ABUS carrier voltage, do not modify
section .text
.global _start
_start:
; establish baseline - test standard x86_64 arithmetic
mov rax, 0x1
mov rbx, 0x2
add rax, rbx ; expected: rax = 0x3
mov rcx, rax
; test subtraction
mov rdx, 0x5
sub rdx, rcx ; expected: rdx = 0x2
; test r-type registers - behavior unknown
mov r1, rax ; does r1 accept a value from rax?
mov r2, rdx ; does r2 accept a value from rdx?
add r1, r2 ; does arithmetic work across r-type?
; test cross-register arithmetic - x86_64 to r-type
mov r3, rbx ; can we move from standard to r-type directly?
; probe a-type registers - expect errors, log the error codes
mov a1, rax ; analog register write attempt
mov a2, r1 ; can r-type feed a-type directly?
; minimal IPC probe - six parameters required, use placeholders
ipc r1, r2, r3, a1, a2, d1 ; six parameters, mixed types
0x60 ; NOP on this architecture
Felix reads over Koko's shoulder and points at the IPC line d1 as the sixth parameter. We are passing the driver class register directly. We do not know if d1 holds anything meaningful yet but it satisfies the parameter count.
Mira The a-type moves are going to throw errors. But the error codes are the data.

Ryo has his finger over the enter key on the log monitor.

Ryo Ready to capture everything. Run it.
Koko clicks the run button
Terminal output - test_001.asm[cortex-as] assembling test_001.asm... [cortex-as] warning: a-type registers are analog-class, behavior undefined without active HAL_ABUS modulation [cortex-as] warning: d1 contains no driver binding, passing null driver context to IPC [cortex-as] assembly complete: 1243 bytes [cortex-run] initializing cortex execution environment... [cortex-run] HAL_ABUS carrier detected at 4.42mV - analog interface active [cortex-run] executing... -- REGISTER STATE AFTER ARITHMETIC -- rax : 0x0000000000000003 OK rbx : 0x0000000000000002 OK rcx : 0x0000000000000003 OK rdx : 0x0000000000000002 OK -- R-TYPE REGISTER STATE -- r1 : 0x0000000000000003 OK [accepted from rax] r2 : 0x0000000000000002 OK [accepted from rdx] r3 : 0x0000000000000002 OK [accepted from rbx] r1+r2 : 0x0000000000000005 OK [arithmetic functional across r-type] -- CROSS-TYPE TRANSFER -- r3 <- rbx OK [standard to r-type: transfer permitted] -- A-TYPE REGISTER STATE -- a1 : 0x0000000000000003 OK [accepted from rax - stored as integer] a2 : 0x0000000000000003 OK [accepted from r1 - stored as integer] [cortex-run] warning: a-type registers received integer values [cortex-run] warning: a-type registers expect analog-class float, integer coercion applied - signal fidelity not guaranteed on HAL_ABUS -- IPC PROBE -- ipc r1, r2, r3, a1, a2, d1 [ipc] parameter count: 6 OK [ipc] r-type parameters: r1 r2 r3 OK [ipc] a-type parameters: a1 a2 OK [integer-coerced, low fidelity] [ipc] driver context: d1 WARN [null driver binding] [ipc] resolving component addresses... [ipc] r1 -> internal address 0x003 OK [ipc] r2 -> internal address 0x002 OK [ipc] r3 -> internal address 0x002 OK [ipc] a1 -> HAL_ABUS channel 0x003 PENDING [awaiting frequency modulation] [ipc] a2 -> HAL_ABUS channel 0x003 PENDING [awaiting frequency modulation] [ipc] d1 -> driver bus SKIP [null context, no transmission] [ipc] status: PARTIAL_EXEC (0xA1) [cortex-run] process exited with code 0xA1

Nobody speaks for three full seconds. Ryo breaks first.

Ryo 0xA1. Not an error. Partial execution. The IPC call ran.
Felix at the wall sheet The a-type registers mapped to HAL_ABUS channels. Channel 0x003. That is an address. The chip has a channel map on HAL_ABUS and we just found the first address.
Mira points at the warning Integer coercion. It accepted our values but it is telling us the fidelity is wrong. The a-type registers want floats. Analog floats. Because they are driving a waveform, not storing a number.
Dani reads the IPC resolution lines carefully Internal address 0x003 for r1. Internal address 0x002 for r2 and r3. The chip has an internal component map and r-type registers index into it. We just learned that this chip has at minimum three internal components addressable by r-type.

Priya is typing rapidly.

Priya The Ljubljana contributor just sent one word in the forum. "PENDING." They are watching the log live and they understood immediately what it means.
Ryo looks at Koko HAL_ABUS channel 0x003 is pending frequency modulation. The chip is waiting. It has accepted the address, it has opened the channel, and it is sitting there waiting for us to send it something it can actually use.

The analog carrier hums at 4.42 millivolts. Felix caps the marker.

Felix We need floating point. And we need frequency. What do we write next?

Koko Let's try to simulate an analog signal and store to an a-type register.

Mira pulls up a new file immediately.

Mira We need to define the waveform mathematically first. A sine wave at minimum. The HAL_ABUS spec said variable frequency, which means we cannot just send a flat value even as a float. We need amplitude and frequency components both.
Ryo already writing The FPU registers. We have not touched them yet. If the chip has x86_64 surface compatibility it should have XMM registers for floating point operations. We use XMM to compute the waveform values and then transfer into a-type.
Felix nods at the wall sheet XMM0 through XMM15 in standard x86_64. Whether they behave identically here is another question but it is the obvious first attempt.

Dani opens the sine wave approximation from the Ljubljana paper.

Dani The Ljubljana paper uses 40 hertz as a baseline frequency for their LFP[12] interface work. That falls in the gamma band, associated with higher cognitive function. It is a reasonable starting point without knowing what frequency the chip actually expects.
Koko - test_analog_001.asm
section .data
carrier dq 4.42
freq dq 40.0 ; 40Hz baseline, gamma band
amplitude dq 3.1 ; minimum threshold voltage we found
pi dq 3.14159265358979
section .text
.global _start
_start:
; load frequency and amplitude into XMM registers
movsd xmm0, [freq] ; xmm0 = 40.0 Hz
movsd xmm1, [amplitude] ; xmm1 = 3.1 mV
movsd xmm2, [pi] ; xmm2 = pi
; approximate one cycle of sine at 40Hz
mov rax, 0x3F999999 ; t = 0.025 as hex float approximation
movd xmm3, eax
mulsd xmm3, xmm2 ; pi * t
addsd xmm3, xmm3 ; 2 * pi * t
mulsd xmm3, xmm0 ; 2 * pi * freq * t
mulsd xmm3, xmm1 ; * amplitude
; attempt transfer to a-type
mov a1, xmm3 ; store computed waveform value to a1
mov a2, xmm0 ; store frequency reference to a2
; IPC with analog parameters
ipc r1, r2, r3, a1, a2, d1
0x60 ; NOP
Felix reads the transfer line mov a1, xmm3. We have never tried moving from an XMM register to an a-type. That could throw an incompatible register class error or it could be exactly what the chip was designed for.
Mira looks at the frequency value 40 hertz is a guess. If the chip rejects it the error code should tell us whether the frequency is wrong or the transfer mechanism is wrong. Two different problems, two different fixes.
Ryo If a1 accepts a float from XMM and the IPC call moves from 0xA1 partial execution to something closer to full execution, we will know the waveform approach is correct.

Priya watches the forum. The Ljubljana contributor and now someone from the TU bioelectronics group are both in the thread, reading in real time. Dani looks at the chip housing.

Dani Channel 0x003 is still pending from the last run. If this chip retains state between executions, it is still waiting.
Felix looks at Koko Run it.
Koko clicks Run again Does not accept xmm register, only physical input.

Mira sits back.

Mira Of course. XMM registers are software abstractions. The a-type registers are not a software concept. They are physical pins on the chip waiting for a physical signal. You cannot compute a waveform in software and hand it over. The waveform has to come from actual hardware.
Ryo What does it say exactly? Does it say incompatible register class or does it say something about physical input required?
Felix already uncapping the marker This changes the entire approach. We cannot fake the analog signal in software at all. The a-type registers are not memory locations. They are direct hardware interfaces. Writing to a1 means putting a physical voltage on a physical pin at a physical frequency.
Dani points at the breadboard The MCP4725 DAC. That is what it is for. We do not write to a-type registers in assembly. We drive them from the DAC directly, set the voltage and frequency externally, and the chip reads the physical signal on the pin and maps it internally to a1, a2, whatever the channel address corresponds to.
Mira So the assembly code cannot touch a-type at all through software. The a-type register state is set entirely by whatever is physically connected to HAL_ABUS. The code can read from a-type, check what signal is present, use it in IPC calls, but it cannot write to it from software.

Ryo looks at the MCP4725 half-assembled on the breadboard.

Ryo We need to finish the interface. The DAC drives HAL_ABUS at the right voltage and frequency, the chip reads the physical signal into a-type registers automatically, and then our assembly code can reference a1 and a2 as inputs rather than trying to write to them.

Felix writes on the wall sheet: "a-type = READ ONLY from software. Physical input only via HAL_ABUS."

Dani looks at Koko The assembly gets simpler actually. We do not need the XMM section at all. We just need IPC to read whatever the DAC is putting on the line.

Priya relays to the forum without being asked. The TU bioelectronics group representative replies within thirty seconds.

Priya They say this is consistent with how biological neural interfaces work in their research. The signal always originates from hardware. Software can listen and respond but it cannot originate an analog biological signal. They say and I am quoting: "you cannot write a heartbeat in assembly."

The room absorbs that. Felix looks at Koko.

Felix Finish the DAC interface. Then we rewrite without the XMM section and let the hardware do what only hardware can do.

Koko together with the others, finishing the DAC interface and rewriting the program

An hour later. The breadboard has been tidied, the jumper wires routed cleanly along the edge. The MCP4725 sits connected between the Raspberry Pi and the chip's interface pins, a small level shifter on a daughter board between them. Felix has taped the schematic to the wall beside the register type columns.

Ryo runs the DAC calibration script. The multimeter reads 4.42 millivolts steady on VOUT.

Ryo Carrier is stable. I am setting the frequency sweep to start at 40 hertz and step upward in 5 hertz increments. We will know we hit the right frequency when the chip responds.
Koko - test_002.asm (rewritten)
section .data
carrier dq 4.42 ; HAL_ABUS carrier, driven by DAC externally
section .text
.global _start
_start:
; verify HAL_ABUS carrier is present
hal d1, HAL_ABUS ; probe analog bus state
; read physical a-type state set by DAC
; a1 and a2 are now hardware inputs, not software writable
mov r1, a1 ; read analog channel 1 into r1
mov r2, a2 ; read analog channel 2 into r2
; verify r-type received signal values
mov rax, r1 ; pull into standard register for inspection
mov rbx, r2
; IPC call with physical analog input
ipc r1, r2, r3, a1, a2, d1
0x60 ; NOP

Mira reads it.

Mira Clean. Eleven lines of actual logic. Everything the a-type registers contain comes from the DAC now, not from us.

Dani checks the level shifter connections one more time.

Dani Confirmed. Physical layer looks good.
Ryo 40 hertz running on DAC. Koko, run the program.
Terminal output - test_002.asm @ 40Hz[cortex-as] assembling test_002.asm... [cortex-as] assembly complete: 412 bytes [cortex-run] initializing cortex execution environment... [cortex-run] HAL_ABUS carrier detected at 4.42mV - analog interface active [cortex-run] executing... [hal] probing HAL_ABUS... [hal] carrier: PRESENT 4.42mV [hal] frequency: DETECTED 40Hz [hal] signal quality: LOW - frequency outside optimal window [hal] status: SUBOPTIMAL (0xB2) -- A-TYPE REGISTER STATE -- a1 : 4.42mV @ 40Hz ACTIVE [physical input confirmed] a2 : 4.42mV @ 40Hz ACTIVE [physical input confirmed] -- R-TYPE AFTER TRANSFER -- r1 : HAL_ABUS_CH_0x003 MAPPED r2 : HAL_ABUS_CH_0x003 MAPPED -- IPC -- ipc r1, r2, r3, a1, a2, d1 [ipc] parameter count: 6 OK [ipc] analog input confirmed on a1 OK [ipc] analog input confirmed on a2 OK [ipc] channel 0x003 : SIGNAL PRESENT SUBOPTIMAL [ipc] status: PARTIAL_EXEC (0xA1) [cortex-run] process exited with code 0xA1
Felix reads the frequency line Suboptimal. Not wrong. 40 hertz is in the window but not the center of it. The chip is telling us to adjust frequency, not abandon the approach.

Ryo is already at the Pi.

Ryo Stepping up. 45 hertz.
@ 45Hz[hal] frequency: DETECTED 45Hz [hal] signal quality: LOW - frequency outside optimal window [hal] status: SUBOPTIMAL (0xB2)
Ryo 55.
@ 55Hz[hal] frequency: DETECTED 55Hz [hal] signal quality: MODERATE - approaching optimal window [hal] status: NOMINAL (0xB1)

Dani exhales.

Dani 0xB1. A new code. We are getting warmer.
Ryo 60.
@ 60Hz[hal] frequency: DETECTED 60Hz [hal] signal quality: MODERATE [hal] status: NOMINAL (0xB1)
Ryo 65.
@ 65Hz[hal] frequency: DETECTED 65Hz [hal] signal quality: HIGH - within optimal window [hal] status: OPTIMAL (0xB0) [ipc] channel 0x003 : SIGNAL OPTIMAL [ipc] status: FULL_EXEC (0xA0)

The room goes completely silent. Priya's hand hits the timestamp key. Felix turns to the wall sheet and writes in large letters: 65Hz - FULL_EXEC. Mira stares at the terminal.

Mira 0xA0. Full execution. IPC completed. The chip just accepted a signal and processed it completely for the first time.
Ryo does not move from the Pi 65 hertz. That is the low gamma band. Associated with attention, working memory, conscious perception.

Dani looks at the chip housing in its container.

Dani Someone designed this chip to respond optimally to the frequency the brain uses when it is paying attention to something.

Nobody speaks for a moment. The donation counter ticks upward. Then again. Priya has not posted anything yet. The Ljubljana contributor and the TU group are both watching the commit log in real time. Felix looks at Koko.

Felix We have full execution on IPC. Channel 0x003 is open and responding. We are inside the chip. a pause What do we do with that?

Koko The SPARCstation? Have it interface with that.

Ryo looks up from the Pi.

Ryo The SPARCstation in Lübeck. We still have not bought it.
Felix already on his phone Calling the seller now.

Mira shakes her head slowly, thinking out loud.

Mira Walk me through the logic before we drive to Lübeck. We have full IPC execution at 65 hertz on channel 0x003. The SPARCstation has register windows, a completely different execution model from anything we have tested. What are we expecting to learn from coupling them?

Dani leans forward.

Dani If the chip has SPARC-like register windows hidden somewhere in the unidentified register types, the SPARCstation bus might provoke a response we cannot get from x86 tooling. A SPARC SAVE instruction causes a register window shift. If the chip recognizes that pattern and responds with a new register namespace, we find register types we cannot find by probing from the x86 side.
Ryo And the SPARCstation is big-endian. Everything we have tested so far assumes little-endian byte order because the x86 surface presentation is little-endian. If any of the deeper register types are big-endian natively, our current tools are reading them backwards and we would never know.

Felix lowers his phone.

Felix Seller picked up. He says it powers on, Solaris boots to a login prompt, the SBus slots are accessible. He wants 40 euros and he cannot ship it, someone has to collect it.

Priya looks at the lab budget spreadsheet.

Priya We have 4,847 euros in the donation fund. 40 euros plus fuel to Lübeck is well within scope. I will log it as hardware acquisition.

Dani looks at the chip housing.

Dani We should also contact the TU bioelectronics group before we go. If the SPARCstation experiment produces a-type activity on new channels we want someone who understands the biological implications in the room when it happens.

Ryo sends a message to the TU group without being asked. Felix looks around the room.

Felix Who goes to Lübeck?
Mira You found HAL. You found IPC. You found the optimal frequency. You should go.
Koko Okay...

Ryo returns to the terminal. Mira reopens the harness script. The opcode spreadsheet is still there from before, half-populated, waiting.

Felix writes "SPARC - tomorrow" on the wall sheet below the 65Hz note.

Dani carefully updates the deviation table with the new findings: IPC confirmed, HAL_ABUS optimal window 65Hz, a-type registers physical input only, channel 0x003 active.

Priya posts the update to the forum. Within two minutes there are eleven responses. The donation counter moves.

The chip housing sits in its container on the central table, closer to Koko than to anyone else. The room sounds like work again: keystrokes, a chair shifting, Ryo reading something quietly to himself.

V · II
The Long Week

The SPARCstation 20 arrives on a Tuesday morning in a cardboard box too large for it, packed with a decade of someone's archived printouts used as padding. Koko sets it on the central table next to the specimen container with the chip housing. Felix tears the box open: the machine is the color of old teeth, that institutional beige of 1990s Sun Microsystems hardware, with its case intact, fan grille dusty but uncracked, and a faded sticker on the front reading "EIGENTUM DES INSTITUTS FÜR PHYSIK".

Mira plugs it in and the machine POSTs, its fan spinning up to a pitch slightly higher than expected as Solaris boots to a login prompt with a blinking cursor. Ryo pulls up a chair while Dani finds a spare monitor cable and Priya opens the SPARCstation 20 hardware reference, as Felix already examines the capacitors through the open case panel with a magnifying loupe.


Koko Let's open this computer first.

Koko finds the flat-head screwdriver in the equipment drawer, the good one with the red handle that everyone uses and nobody puts back. The SPARCstation 20 opens differently from modern hardware. Four Phillips screws on the back, then the top panel slides forward and lifts off as a single piece. It takes a moment to figure out the direction.

Inside the machine, the motherboard is clean by the standards of a thirty-year-old computer, no visible corrosion, no catastrophic leakage. The layout is dense and logical in the way 1990s engineering often was, everything serving a purpose, nothing wasted. Two SIMM slots, both populated. A SCSI ribbon cable running to a hard drive that is probably the original. The CPU module, a hyperSPARC, sits under a heatsink held in place by a spring clip.

Felix moves the loupe slowly across the board, starting at the power regulation cluster.

Felix Two of the four near power regulation show visible bulging on the tops. Not leaking yet but close. The other two look okay from the outside but that means nothing on hardware this age.
Dani pulling up an ESR meter[17] from the component cabinet We test all twelve before we replace anything. A visually good capacitor can still be electrically dead.
Felix keeps the loupe moving NVRAM[18] chip is here. a pause Yes. Pin 12. Bent almost flat against the body of the chip. Whoever had this before bent it getting the chip out and bent it back imprecisely. It is making contact by surface tension essentially.
Mira Can it be straightened?
Felix quiet for a moment, looking at it Once. Maybe. Chip pins at this age are brittle. If we try to straighten it and it snaps we need the replacement chip ready before we touch it. And even if it holds, a pin that has been bent twice on a thirty-year-old NVRAM is not a pin you trust.

Ryo is already searching the component database.

Ryo M48T08 or M48T12 depending on the board revision. checks the reference This one takes the M48T08. Still manufactured. Mouser has them in stock, three-day shipping.

Priya adds it to the order queue without being asked. The machine sits open on the table, its thirty-year interior visible to the afternoon light coming through the lab's single large window.

Dani Order the chip, test the capacitors, then decide whether to attempt the pin or go straight to replacement?

Koko Let's test the capacitors and first test if we can bend the pins.

They work through the board methodically, Koko placing the ESR leads, everyone else watching the meter and logging the readings. Ryo writes each result in the shared document in real time.

Ryo Power regulation cluster: first cap, 4.2 ohms, borderline. Second cap, 11.7 ohms, dead. Third cap, 3.8 ohms, borderline. Fourth cap, 0.6 ohms, good. CPU cluster: first cap, 0.4 ohms, good. Second, 0.9 ohms, good. Third, 6.1 ohms, dead. I/O cluster: 0.5, 0.7, 0.4, 1.1, 8.3. Four good, one dead.
Felix Three confirmed dead, two borderline that will fail within a year. Replace all five as a minimum. Sensible to replace the borderlines too while the board is already out.

Priya updates the component order. Seven capacitors, values and ratings from the datasheet. Then Koko moves to the NVRAM chip. Finds the bent pin. Looks at it for a moment. Finds the smallest flat-head in the drawer, the one with the yellow handle. Very carefully, applies pressure to the pin.

A sound that is not loud but is very final. The pin does not bend. It separates from the body of the chip cleanly, as if it had been waiting for permission.

Dani How critical is pin 12 on the M48T08?
Ryo checks the datasheet without being asked, quietly Pin 12 is VCC. That is the power supply pin.
Mira So the chip has had no reliable power delivery since whoever bent that pin put it back.
Felix Which means the NVRAM contents, the hostid, the ethernet address, the OpenBoot configuration, everything stored on that chip, may or may not have survived depending on the internal battery.

The broken pin sits on the motherboard, a small silver fragment next to the chip body. Priya adds the M48T08 to the component order and marks it urgent.

Priya Three-day shipping becomes express. It arrives Thursday.
Felix We cannot reinstall Solaris until the NVRAM has a valid hostid. The installer reads it during setup. We can work on the capacitors while we wait for Thursday.

They bring protective equipment and a soldering iron to the bench. Dani clears the space and lays down an antistatic mat. The iron, a temperature-controlled station, the tip clean from the last session, heats to 320 degrees Celsius. Mira prepares the replacement capacitors on a strip of antistatic foam, each with its value written in marker on a small piece of tape beside it. Priya photographs the board before anything is touched, three angles, close-up on each capacitor position.

The first capacitor, the dead one in the power regulation cluster, comes off cleanly. The pad is intact. Good. The second takes longer, flux-bonded, shifting slightly before releasing. The pad holds. The CPU cluster capacitor reveals a faint shadow of corrosion on the pad beneath, not structural damage but the beginning of one.

Felix Clean that pad thoroughly before the new cap goes on. Isopropyl and a cotton swab.

They work through all seven. The fume extractor hums steadily. The lab smells of flux and hot metal. Ryo documents each completed joint in the shared log.

Ryo Seven replacements complete. All joints visually clean. No lifted pads, no bridging.
Dani running the ESR meter across all seven new capacitors 0.3, 0.4, 0.4, 0.6, 0.3, 0.5, 0.4. All within spec.

The board sits on the antistatic mat, seven fresh solder joints slightly shinier than the old ones, the new work identifiable from the old. Two days until Thursday.


Koko Yeah, let's read the Solaris reinstallation process.

Ryo pulls up a chair to the main workstation and opens a browser. Mira sits beside him.

Ryo Solaris 2.6 is the last version officially supported on the SPARCstation 20. The installation process on SPARC hardware is not like x86. There is no BIOS in the conventional sense. The machine boots through OpenBoot, stored partly in the NVRAM. Before we can install anything, OpenBoot needs to be functional and the NVRAM needs a valid hostid and ethernet address.
Mira Which is why Thursday matters. Without the M48T08 we cannot even get to the installer.
Ryo scrolling through the archived Sun documentation Once the NVRAM is in and programmed, the boot sequence goes like this. We boot from installation media. The SPARCstation 20 has a CD-ROM drive, assuming it works. If the drive is dead we boot from the network using TFTP, which is more complicated but documented. We prepare for network boot as the primary method. The network boot process requires a TFTP server on the local network serving the boot image and an NFS server serving the installation filesystem.
Felix The drive was not mentioned in the listing either way. Assume it is dead until proven otherwise.
Ryo The installer is text-based. Timezone, locale, disk partitioning, network configuration, package selection. On this hardware the full installation takes approximately forty minutes. pause There is one complication. The Solaris 2.6 installation media is not freely available. It was commercial software. There are archived copies on archive.org, the legality of which is ambiguous given that Oracle has not actively pursued enforcement since acquiring Sun in 2010.
Mira We are reverse-engineering a chip implanted in a human brain by a genetics institute that refuses to release its instruction set. I think we can accept some ambiguity around a 1997 operating system license.
Koko Yes, let's go on archive.org, and I think we can also try with QNX 6.4.1 if we have a computer that old. You know, live CD only, because installing QNX requires a license key that is impossible to obtain.

Koko opens archive.org. The results come back immediately. Two relevant entries at the top.

Ryo There it is. Two copies. The May 1998 edition, identifier sol-2.6_598-installation-sparc-x86, uploaded 2022. It includes the SPARC installation ISO at 538 megabytes, a maintenance update, and the documentation disc. The second is the Desktop SPARC edition, identifier solaris26desktop, uploaded 2019 with a verified SHA1 checksum.
Felix Take the second one. It has a checksum we can verify.
Priya Downloading now. 538 megabytes. Twenty minutes approximately.

Felix looks up from the hardware reference at the QNX suggestion.

Felix QNX 6.4.1 is x86 only. It was never ported to SPARC. The SPARCstation runs big-endian SPARC V8 architecture. QNX Neutrino[19] at version 6 supports x86, some ARM, some MIPS. Not SPARC. It would not boot on this hardware at all.
Dani There was a QNX 4 port to SPARC in the early 1990s. But QNX 4 is even harder to source than Solaris 2.6 and the toolchain is essentially extinct. If you want to run QNX 6.4.1 we would need a separate x86 machine.

Everyone looks at Priya. Priya manages the lab's hardware inventory.

Priya without looking up from the download monitor There is a Pentium 4 tower in the storage room that nobody has claimed. It was donated in the first month. I do not know if it works.
Dani QNX is a real-time operating system. Deterministic scheduling, microsecond timing guarantees. If we ever need to generate precise analog signals for the HAL_ABUS interface, QNX would give us timing accuracy that Linux cannot match due to its non-deterministic kernel.
Felix slowly That is actually a good reason. Not for Thursday. But eventually.

Koko retrieves the Pentium 4 from the storage room, connects it to a spare monitor, and presses the power button.

The fans spin up at full speed immediately. Not the gradual spool-up of a normal POST. All of them, full speed, the sound of a machine trying very hard. The monitor flickers. A solid red screen appears, filling the entire display, white text in a font that is clearly not a standard BIOS output but a manufacturer's embedded diagnostic firmware.

Manufacturer diagnostic firmware - critical failureHARDWARE INTEGRITY CHECK - CRITICAL FAILURE Manufacturer Diagnostic Firmware v2.1.4 ===================================================== FATAL: Multiple critical component failures detected. System cannot proceed to POST. COMPONENT STATUS REPORT: ----------------------------------------------------- CPU : FAIL - thermal sensor reads 94°C at idle possible heatsink separation or compound degradation RAM SLOT A : FAIL - no response from DIMM, possible physical damage RAM SLOT B : WARN - DIMM detected, integrity uncertain RAM SLOT C : FAIL - no response from DIMM RAM SLOT D : FAIL - no response from DIMM GPU : FAIL - PCIe device not enumerated HDD : FAIL - no device detected on primary IDE OPTICAL : FAIL - no device detected on secondary IDE PSU RAIL +12V : WARN - reading 10.8V (expected 12V ±5%) PSU RAIL +5V : WARN - reading 4.6V (expected 5V ±5%) PSU RAIL +3.3V: OK - reading 3.31V CMOS BATTERY : FAIL - battery voltage below threshold SUMMARY: 6 CRITICAL, 3 WARNING, 1 OK ----------------------------------------------------- This system has sustained severe physical damage. Do not attempt to operate. Press F2 to view extended diagnostics. Press F10 to attempt emergency boot (NOT RECOMMENDED). =====================================================
Mira reading from across the room CPU at 94 degrees at idle. The heatsink has separated. If they had tried to run this for more than a few minutes it would have throttled immediately and then shut down.
Dani walks over and looks at the dent on the left panel That dent is at exactly the height of the GPU slot. Someone dropped this or it was dropped for them. The GPU took the impact and transferred it through the slot into the board.
Ryo quietly It was donated. Someone donated a machine that had been thrown away. Perhaps literally.

Koko Let's open up the Pentium 4.

The side of the case swings open on a hinge stiff from the dent warping the frame.

The heatsink is present but sitting at a visible angle, one of its four push-pin clips broken, the others holding it loosely. The thermal paste between the heatsink base and the CPU lid has dried to a grey powder and cracked in several places, the gap visible to the naked eye. The GPU slot is worse. The card is still in the slot, a mid-range card from around 2005, but the connector is visibly cracked along the bottom edge, one corner pushed downward at an angle the slot was not designed to accommodate. The RAM slots reveal a bent contact pin in slot A, and slots C and D hold no DIMMs at all.

Ryo checks the board identifier D865PERL. Intel desktop board, 2003, Socket 478. AGP slot, not PCIe. The diagnostic firmware misidentified it.
Mira Which means the slot damage report may also be inaccurate. If it is misidentifying the slot type it may be misreporting the damage severity.
Felix examining the AGP slot The slot retaining clip is bent outward but the slot contacts look intact. The card shifted in the impact but the slot itself may have survived. We test with a known working AGP card before assuming the slot is dead. Push-pin coolers. with the expression of someone who has opinions about push-pin coolers Three of four still holding. The broken one is the front-right. We can replace the entire cooler for almost nothing.
Koko Let's invest in it, we cannot waste machines.
Felix nods once, with the approval of someone who has the same instinct List of parts then.

Dani examines slot A under the magnifying loupe, then very carefully uses a mechanical pencil with the lead retracted as a probe, applying pressure in small increments against the bent contact pin, checking the angle after each pass. Forty seconds of absolute stillness in the lab.

Dani straightening up It is at about 10 degrees now. Acceptable. The DIMM will seat and make contact.
Ryo Total parts cost estimate: CPU cooler, 5 to 8 euros second-hand. RAM, 3 to 5 euros for a 512 megabyte DDR400 stick. PSU, 20 euros new or 8 euros second-hand. Thermal paste, we already have it. AGP card, already have it. Pin repair, done. 35 euros maximum. Possibly 15 if we source everything second-hand.
Felix opens the bottom drawer of the component cabinet There is an old Radeon 9250 in here from a previous donation. AGP, low power, no external connector needed. We use it to test the slot and keep it as the permanent GPU if the slot passes.

Priya places the order and updates the budget log. Felix looks at the two open machines, the SPARCstation with its fresh capacitors and broken NVRAM, the Pentium 4 with its dented panel and rebuilt RAM slot.

Felix We close it up, set it aside, and come back to it Saturday after the Altona market. Thursday the NVRAM arrives. Friday the SPARCstation gets its chip and we begin Solaris. The Pentium 4 runs QNX by the following week at the latest.

Then, without warning, a small explosion from the SPARCstation occurs at the end of the bench. The sharp crack immediately comes with an acrid and chemical smell. A thin curl of grey smoke rises from inside the open case, from the power supply unit at the back right corner. Felix moves first, reaching past Koko and pulling the power cable from the wall socket in one motion. The fans spin down. The smoke thins and stops.

Dani leaning over the open case with the loupe PSU capacitor. The large electrolytic on the primary side, closest to the AC input, has vented. The top is open, you can see the electrolyte residue around the base.
Mira Check the board. If the PSU capacitor vented it may have sprayed electrolyte onto the motherboard or the CPU module during the event.
Dani There is residue on the edge of the CPU module. Not heavy. The module is socketed so we can remove it and clean it. The board surface underneath looks clear from this angle but we need to remove the PSU to see properly.
Ryo looking up the SPARCstation 20 PSU specification The SPARCstation 20 uses a proprietary Sun power supply. Not standard ATX. Sun part number 300-1077. searches Three listings on eBay. One in the UK, 45 euros plus 12 shipping. Five to seven business days.
Dani If the PSU was running under stress before it vented, the new capacitors we installed may have been operating outside spec. We test every capacitor again once the PSU is replaced and the machine is stable.

Priya places the PSU order with the UK seller and updates the budget log.

Priya Between the NVRAM, the capacitors already installed, the PSU, and the Pentium 4 parts, we have spent 143 euros of the donation fund so far. The fund currently holds 5,340 euros. Someone donated while we were working.
Koko There is always something with older hardware and being independent.
Ryo The Institute has a climate-controlled server room, humidity regulated to within two percent and a temperature held at 18 degrees Celsius year-round. Every machine on a UPS and a facilities team that replaces capacitors before they fail because they run predictive maintenance software that costs more per year than our entire donation fund.
Mira And rack-mounted incubator units for the biological samples, filtered air, redundant power feeds from two separate grid connections. If one transformer fails the other takes the load in under 200 milliseconds.
Felix looking at the burnt PSU We have a capacitor that exploded because someone ran a 30-year-old computer without checking the power supply first.
Priya AntiX Linux[20] on everything. Not because we chose it philosophically, but ecause AntiX is the only distribution that will run on hardware this old without swap thrashing. The newest machine in this lab is eight years old and the oldest is fifteen.
Dani Their Arduino components are medical grade. When a pin reads 3.3 volts it is 3.3 volts to four decimal places. Ours read approximately the right voltage and we cross-check with the multimeter because we do not fully trust any individual component.
Koko Why hasn't the Institute equipped our formerly empty university with newer computers and components and we had to purchase a lot of stuff ourselves? When they built Siedlischte, they decided to waste taxpayer money building this university we are in.
Ryo Because equipping the university well was never the point. The university was built to demonstrate that the Institute supports the generated human community. A building with classrooms and a name above the door is a photograph and a functional research institution with proper equipment is a commitment.
Felix The press release when they announced the university said "state of the art facilities for the generated human community". There was a photograph of the building exterior. Nobody asked what was inside.
Dani It is the same logic as the chip. Give enough to demonstrate existence but not enough to enable independence. The university exists so the Institute can say it exists. If the university actually produced meaningful research that challenged the Institute, it would have been better equipped.
Priya The Cortex Project donation counter is at 5,340 euros. None of it came from the Institute or the university budget. The university budget, as far as anyone can determine, covers the electricity and the building maintenance contract.
Felix A functioning server room would cost the Institute approximately 40,000 euros to equip properly for this space. That is six weeks of their genomic analysis software licensing fees. It was a decision, not a constraint. looks at the two broken machines The SPARCstation cost 40 euros. The DAC cost 6. The Raspberry Pi was already here. The chip housing was donated by someone who had it surgically removed and chose to give it to us rather than keep it. We are running a research project that the Institute's entire infrastructure was designed to make impossible, on hardware they decided we did not deserve, and we are ahead of them.
Dani looking at the donation counter Someone just gave 500 euros. The note says: "I am a generated human. I am 22 years old. This is everything I have saved this month. Please keep going."

Nobody speaks for a moment. The wall sheet is visible from where everyone is sitting.


On Thursday, the NVRAM chip arrives in a small antistatic bag inside a padded envelope from a components distributor in the Netherlands. The PSU from the UK seller reaches the university mailroom on Friday. On Saturday morning, Ryo and Mira take the U-Bahn to the Altona electronics market and return with a Socket 478 cooler, two sticks of DDR400 RAM, a replacement PSU for the Pentium 4, and a bag of assorted thermal paste syringes a vendor threw in for free.

Later, on Monday morning, both machines are open on the bench. The reassembly takes most of the morning. PSU first, then CPU module reseated on the SPARCstation after full isopropyl cleaning, then a second ESR pass on all seven new capacitors confirming they survived the venting event, then the M48T08 seated carefully into its socket. On the Pentium 4: new PSU, new cooler with fresh thermal paste, two DDR400 sticks in slots B and D, the Radeon 9250 slotted into the graphics port.

After several hours of work, both machines are ready.

Koko pointing at the Pentium 4 The Windows 98 five dollar PC.
Felix Michael MJD. a short laugh His was a Celeron at 1 gigahertz in a Gateway micro-ATX case. Ours cost 40 euros from a man in Lübeck who described it as "powers on, makes sounds".
Ryo MJD's at least booted on its own. Ours needed a new PSU, a new cooler, two RAM sticks, a pin straightened with a mechanical pencil, and a trip to Altona before it would show anything other than a red screen.
Mira His has been running since 2016. He has installed Windows Vista on it. Windows 7. French Windows 98. A GeForce FX 5200. Ours is going to run QNX 6.4.1 live from a CD and drive a DAC at 65 hertz to talk to a chip implanted in a human brain. a pause I think we win.
Priya His cost five dollars. Ours cost 40 euros plus parts. He also did not have to straighten a RAM slot pin with a mechanical pencil in a university built by an institution that did not bother to furnish it.
Koko Now let's run QNX on the five-dollar PC and install Solaris on the SPARC.

Koko pulls the QNX 6.4.1 live CD from its sleeve. Burned two days ago from an archive image, verified, labeled in Priya's handwriting: QNX 6.4.1 LIVE - CORTEX PROJECT. Felix opens the Pentium 4's optical drive bay. Koko presses the power button.

No red screen this time. The fans spin up at a normal pace. A single clean POST beep. The BIOS splash appears, then the boot sequence begins reading from the optical drive.

Dani watching the screen It sees the disc.

A loading bar appears, QNX's distinctive boot progress, minimal, grey on black, moving steadily. The desktop appears: QNX's Photon microGUI, lightweight, loading in seconds on hardware this old.

Felix quietly, with satisfaction It works.

Meanwhile Ryo moves to the SPARCstation and powers it on. The Sun logo appears on screen, white on black. The POST runs and then OpenBoot's prompt appears.

OpenBoot - SPARCstation 20Sun Microsystems Inc. SPARCstation 20 OpenBoot 2.25, 64 MB memory installed, Serial #XXXXXXXX Ethernet address X:X:X:X:X:X, Host ID: XXXXXXXX ok
Ryo The NVRAM is reading. Host ID is there. Ethernet address is there. The M48T08 is working.

Mira exhales. Felix reads the memory line: 64 megabytes, both SIMMs reading correctly. Ryo types at the OpenBoot prompt.

OpenBoot - network boot configurationok setenv boot-device net boot-device = net ok setenv diag-switch? false diag-switch? = false ok boot net Booting from: net Boot: /inetboot.SunOS_5.6.sun4m SunOS Release 5.6 Version Generic [UNIX(R) System V Release 4.0] Copyright (c) 1983-1997, Sun Microsystems, Inc. All rights reserved. Configuring network interface... Starting Solaris Installation Program...

The text-based installer. Koko takes the keyboard.

Solaris 2.6 installer - network identificationSolaris Interactive Installation ───────────────────────────────── Identify This System Host name: [ cortex-sparc ] IP address: [ 192.168.1.42 ] Subnet mask: [ 255.255.255.0 ] IPv6: ( ) Yes (*) No Default route: [ 192.168.1.1 ] Name service: (*) None [F2 Continue]
Time zone (*) Europe / Germany / Europe/Berlin [F2 Continue]
Date and time Year: [2026] Month: [05] Day: [22] Hour: [14] Minute: [37] [F2 Continue]
Dani The NVRAM battery is dead, it defaulted to 1970. Koko corrected it.
Software selectionSelect the Solaris software to install on the system. ( ) Entire Distribution plus OEM Support (998 MB) ( ) Entire Distribution (834 MB) ( ) Developer System Support (762 MB) ( ) End User System Support (512 MB) (*) Core System Support (259 MB) ( ) Custom Installation [F2 Continue]
Ryo The entire distribution needs 834 megabytes. The drive has 535. Core System Support at 259 fits comfortably. We install core, then bring in packages manually from the documentation disc over NFS.
Disk and filesystem layoutDisk c0t3d0 - 535 MB - selected Preserve existing data? (*) No - Overwrite existing data Auto Layout: Mount Point Size / 20 MB /usr 200 MB /export/home 30 MB swap 64 MB (free) 221 MB [F2 Continue]
Installation profile System name: cortex-sparc Install type: Initial Installation Software: Core System Support (259 MB) Disk: c0t3d0 Time zone: Europe/Berlin WARNING: All data on c0t3d0 will be erased. [F2 Begin Installation]

A short pause. Everyone reads the summary. Mira nods. Dani says press it. Koko presses F2.

Installation progress Checking disk... Done Creating Solaris disk label... Done Creating and checking UFS file systems... Done Mounting file systems... Done Installing packages from network... SUNWcsr (Core Solaris, Root) [=====> ] 23% SUNWcsr (Core Solaris, Root) [==========> ] 43% SUNWcsr (Core Solaris, Root) [=========================>] 100% Done SUNWcsu (Core Solaris, Usr) [=============> ] 61% SUNWcsu (Core Solaris, Usr) [=========================>] 100% Done Installation complete. Packages installed: 47 Disk space used: 261 MB Disk space available: 219 MB Errors: 0 The system will reboot from c0t3d0 in 5 seconds.

The SPARCstation reboots from its own drive for the first time under their ownership. The Sun logo appears. OpenBoot hands control to the Solaris kernel. Boot messages scroll past, devices attaching, file systems mounting, services starting.

Solaris 2.6 - first bootSun Microsystems Inc. SunOS 5.6 Generic August 1997 cortex-sparc console login: _
Felix to Koko Log in.
Koko logs in as root, sets a root password, verifies the network interface and disk space, then mounts the NFS share and installs the development tools: SUNWgcc, SUNWgmake, SUNWbinutils, SUNWsprot
Compiler and toolchain verification# gcc -o /tmp/hello /tmp/hello.c # file /tmp/hello /tmp/hello: ELF 32-bit MSB executable, SPARC, version 1, dynamically linked # /tmp/hello cortex-sparc online # which as /usr/ccs/bin/as # as --version GNU assembler 2.8.1 (sparc-sun-solaris2.6)
Dani 32-bit MSB SPARC. Big-endian confirmed. Everything this machine generates will be byte-swapped relative to our x86 workstations. We need to keep that in mind when we compare output across architectures.
Felix to Koko Good work today.

Koko Now it's time to insert our implant to the SPARC.

The room reorganizes itself around the central table. Priya closes the forum tab without being asked. Dani moves two laptops off the table. Ryo wheels the DAC interface from its corner position to the table beside the SPARCstation. Felix spreads an antistatic mat across the cleared center of the table. Then everyone looks at the specimen container.

Felix pulls on nitrile gloves. He hands a pair to Koko without speaking.

Ryo The SBus slots on the SPARCstation 20 run at 25 megahertz, 5 volt TTL logic. HAL_ABUS operates at 4.42 millivolts. Direct connection would destroy the chip immediately. The bridge goes through the level shifter stack we built for the DAC interface, extended with a custom SBus breakout we wired yesterday. The SBus carries the SPARC bus signals. The breakout samples them, the level shifter drops them to millivolt range, and the chip sees something that approximates what it expects on HAL_ABUS.

Dani checks each wire connection against the diagram taped to the inside of the case. All 96 SBus lines accounted for. The DAC is running. The multimeter reads 4.42 millivolts on VOUT. 65 hertz on the frequency generator.

Felix Your discovery, your hands.

Koko lifts the specimen container and sets it on the antistatic mat. Opens the lid. The chip housing is smaller than it looks in photographs, roughly the size of a large thumbnail, matte grey, its pin array visible on the underside. Priya photographs it before anything else is touched. Koko places it in the interface cradle Ryo fabricated from a ZIF socket base and two strips of brass shimstock. The cradle holds it without pressure, contact made through the shimstock touching the perimeter pins.

Ryo checks the contact points with the multimeter HAL_ABUS lines reading continuity. r-type address lines reading continuity. d1 driver line is open. Expected, we are not using a driver class device on this side.

Koko connects the final wire, the analog carrier line from the DAC output to the chip's HAL_ABUS pin, a single fine-gauge wire terminated in a micro-clip. The clip seats. The multimeter on the carrier line reads 4.42 millivolts.

The root prompt blinks on cortex-sparc. The donation counter ticks up on Priya's screen. Someone is watching the commit log right now.

Koko sits down at the SPARCstation keyboard and sends arbitrary commands to the implant chip, watching the oscilloscope display Ryo has connected to the HAL_ABUS monitoring line
cortex-sparc - initial SPARC test# cat > /tmp/test_save.s .section ".text" .global main main: save %sp, -96, %sp mov 0x1, %l0 mov 0x2, %l1 add %l0, %l1, %l2 restore retl nop ^D # as -o /tmp/test_save.o /tmp/test_save.s # ld -o /tmp/test_save /tmp/test_save.o # /tmp/test_save #

The oscilloscope shows a response on HAL_ABUS. A brief perturbation in the carrier signal.

Dani reading the oscilloscope There. 3 milliseconds after the SAVE instruction executed. The carrier amplitude modulated slightly. 4.42 dropped to 4.38 and recovered.
Felix That is 40 microvolts of response. The chip reacted to the register window shift.

Koko writes a second test with three SAVE and three RESTORE calls. The oscilloscope shows six perturbations, three rising on SAVE, three in the opposite direction on RESTORE. But the spacing between them is irregular. Ryo stares at the timing display.

Ryo The three SAVE events should be equidistant in time. The instructions are identical. But look at the spacing. 847 microseconds between event one and two. 1,203 microseconds between event two and three. That is not the chip. That is Solaris. Kernel scheduling interrupts. Between our instructions executing, the kernel is doing other things. The CPU is not exclusively ours.
Mira Which means the signal the chip is receiving is not a clean sequence of register window shifts at consistent intervals. Every kernel interrupt between our instructions is arriving on HAL_ABUS as an unexpected timing event. The chip may be interpreting the timing irregularity as signal content.

Ryo turns and looks at the Pentium 4.

Ryo QNX.
Koko I will, let's write on the QNX.

Koko takes the chair at the Pentium 4. Ryo pulls a second chair beside it. They write the measurement harness together, Ryo dictating structure, Koko typing, both arguing over specifics.

QNX - cortex_measure.c (HAL_ABUS measurement harness v0.1)
#include <stdio.h>
#include <stdlib.h>
#include <pthread.h>
#include <sched.h>
#include <sys/neutrino.h>
#include <sys/syspage.h>
#include <sys/mman.h>
#include <hw/inout.h>
#define LPT1_BASE 0x0378
#define LPT1_STATUS (LPT1_BASE + 1)
#define STATUS_BIT4 (1 << 4)
#define LOG_PATH "/tmp/cortex_events.log"
#define MAX_EVENTS 65536
typedef struct {
uint64_t timestamp_cycles;
uint8_t status_byte;
uint8_t event_type; /* 0 = rising edge, 1 = falling edge */
uint8_t reserved[6];
} cortex_event_t;
static cortex_event_t event_log[MAX_EVENTS];
static volatile int event_count = 0;
static uint64_t cps; /* cycles per second */
void *measure_thread(void *arg) {
struct sched_param sp;
uint8_t prev_status, curr_status;
uint64_t t;
/* elevate to real-time FIFO scheduling, priority 63 */
sp.sched_priority = 63;
pthread_setschedparam(pthread_self(), SCHED_FIFO, &sp);
mlockall(MCL_CURRENT | MCL_FUTURE);
ThreadCtl(_NTO_TCTL_IO, 0); /* I/O privilege for direct port access */
prev_status = inb(LPT1_STATUS) & STATUS_BIT4;
printf("[cortex] measurement loop active\n");
printf("[cortex] polling LPT1 STATUS bit 4\n");
printf("[cortex] cycles/sec: %llu\n", (unsigned long long)cps);
while (event_count < MAX_EVENTS) {
curr_status = inb(LPT1_STATUS) & STATUS_BIT4;
if (curr_status != prev_status) {
t = ClockCycles();
event_log[event_count].timestamp_cycles = t;
event_log[event_count].status_byte = inb(LPT1_STATUS);
event_log[event_count].event_type =
(curr_status > prev_status) ? 0 : 1;
event_count++;
prev_status = curr_status;
}
}
return NULL;
}
int main(int argc, char *argv[]) {
pthread_t tid;
pthread_attr_t attr;
cps = SYSPAGE_ENTRY(qtime)->cycles_per_sec;
printf("[cortex] HAL_ABUS measurement harness v0.1\n");
printf("[cortex] Cortex Project - University of Siedlischte\n");
pthread_attr_init(&attr);
pthread_attr_setinheritsched(&attr, PTHREAD_EXPLICIT_SCHED);
pthread_attr_setschedpolicy(&attr, SCHED_FIFO);
pthread_create(&tid, &attr, measure_thread, NULL);
pthread_join(tid, NULL);
write_log();
return 0;
}
Ryo The polling loop has no sleep, no yield, no interruption. On a real-time FIFO thread at priority 63 it will consume the entire CPU core. That is intentional. We want nothing else running between our inb() calls.
Felix LPT1. to Koko Did you know that LPT is a reserved name in Windows?
Koko Yeah, I knew.
Felix LPT1 through LPT9 are reserved device names in Windows. COM1 through COM9 as well. CON, PRN, AUX, NUL. You cannot create a file named LPT1.txt in any Windows directory regardless of the extension. The operating system intercepts the name before the filesystem sees it. A very old design decision that has never been cleaned up.
Ryo On our AntiX machines LPT1 is just /dev/lp0. No reservation, no interception. One of the small ways Linux is less haunted by its own history.

Dani holds out the comparator output wire. Koko takes it and connects the comparator output to LPT STATUS pin 13. A small brass hook terminal, a single clip, seated.

Dani About the leader thing, so as to know. You found HAL. You found IPC. You wrote the measurement harness. You are going to Lübeck for the SPARCstation. We are not designating you. We are just accurate.

Koko starts the measurement harness on QNX. Ryo runs the SAVE sequence on the SPARCstation simultaneously.

QNX - cortex_measure output[cortex] HAL_ABUS measurement harness v0.1 [cortex] Cortex Project - University of Siedlischte [cortex] initializing... [cortex] measurement loop active [cortex] polling LPT1 STATUS bit 4 [cortex] cycles/sec: 2793000000 [cortex] 6 events captured [cortex] log written to /tmp/cortex_events.log
QNX - /tmp/cortex_events.log# CORTEX PROJECT - HAL_ABUS event log # cycles_per_sec: 2793000000 # columns: index time_sec time_cycles status_byte event_type 0 0.000082341 229,974,513 0x78 RISING ; SAVE window 1 1 0.000082447 230,271,271 0x58 FALLING 2 0.000082559 230,583,687 0x78 RISING ; SAVE window 2 3 0.000082661 230,869,273 0x58 FALLING 4 0.000082774 231,185,901 0x78 RISING ; SAVE window 3 5 0.000082881 231,484,117 0x58 FALLING ; event spacing (RISING to RISING): ; event 0 to 2 : 218 microseconds ; event 2 to 4 : 215 microseconds ; event 4 to 6 : 215 microseconds ; jitter : 3 microseconds

The room reads the log in silence.

Mira Three microseconds of jitter. Down from 391 microseconds on Solaris.
Felix reading the rising-to-falling width Each event lasts approximately 106 microseconds. The chip responds to a SAVE instruction with a 106-microsecond pulse on HAL_ABUS. Consistent across all three windows. That is a response characteristic.
Dani 106 microseconds. We can now say with confidence that the chip's HAL_ABUS response to a SPARC register window shift is 106 microseconds wide, repeatable, at 3 microseconds jitter on our current hardware.
Priya typing the forum update What do I say this time?
Ryo Say that QNX on a five-dollar Pentium 4 repaired from a red screen of death is producing sub-microsecond timing measurements of a proprietary biological interface chip using a parallel port and a voltage comparator. And that it is working.

The forum posts. Priya watches the replies come in. Then one from the Ljubljana contributor.

Priya reading aloud, very quietly "We found it too. From the biological side. Same number. 106."

Nobody moves for a moment.

Dani They measured 106 microseconds from neural tissue response data in their LFP interface research. Without knowing what we were measuring. From the opposite direction.
Ryo sits down The chip's HAL_ABUS response time matches the characteristic timescale of a SPARC register window shift as measured by a neural LFP interface. Someone designed this chip specifically to communicate with biological tissue at the timescale of SPARC register window operations.
Dani very quietly The Institute did not build a memory chip. They built a SPARC coprocessor for the human brain.

Felix uncaps the red marker and writes beneath 65Hz - FULL_EXEC:

106μs - SPARC WINDOW = LFP RESPONSE

The chip housing sits in its cradle, the carrier humming at 4.42 millivolts, 65 hertz, connected to both machines. The lab is three months old and now it feels even older.

V · III
The Paper

The paper takes eleven days of intense writing and collaborative debates. Initially divided on where to submit, the argument is resolved when Priya secures TU bioelectronics and Ljubljana researchers as co-authors, shifting the focus to a joint submission to Frontiers in Neuroscience. Koko drafts the technical section, Ryo refines the methodology, and Mira handles the results, while Dani fights in tracked changes for three days to keep the word "deliberate" in the description of the Institute's design choices. The TU group provides the biological correlation linking the 106-microsecond window to LFP data, and after five drafts from Felix, the non-technical summary is finalized.

Two weeks after their first debate, the paper is finally ready. The lab gathers at the central table, surrounded by the specimen container and a wall sheet covered in data, as Priya opens the submission portal to enter the final details.

Priya reads the title aloud one final time "Cortical Port Architecture in Proprietary Neural Interface Chips: Hardware Characterization, Instruction Set Partial Disclosure, and Biological Response Correlation - A Reverse Engineering Study."
Felix It is long.
Priya Academic titles are long.

She submits.


CORTEX PROJECT RESEARCH PAPER - PREPRINT
Submitted to Frontiers in Neuroscience / Neural Interface Engineering (proposed specialty section)
Source code, raw data, and replication instructions: https://git.cortexproject.siedlischte.de/cortex/chip-re
DOI: pending peer review
K. [Koko] · M. [Mira] · F. [Felix] · R. [Ryo] · D. [Dani] · P. [Priya]
University of Siedlischte IT Lab
+ Ljubljana Bioelectronics Research Group (3 authors)
+ TU Hamburg Bioelectronics Laboratory (2 authors)
Cortical Port Architecture in Proprietary Neural Interface Chips: Hardware Characterization, Instruction Set Partial Disclosure, and Biological Response Correlation - A Reverse Engineering Study
Abstract
We report the first systematic hardware characterization of the proprietary neural interface chip implanted in printed generated humans by the Institute of Genetics. Through reverse engineering conducted on a surgically donated chip specimen, we identify a modified x86-64[21] instruction set surface presentation overlaying a multi-architecture register file incorporating elements of SPARC, MIPS, and IBM Z coprocessor conventions. We document previously undisclosed instruction mnemonics including HAL and IPC, characterize the analog bus interface HAL_ABUS operating at 4.42 millivolts carrier voltage and 65 hertz optimal frequency, and measure a characteristic 106-microsecond response window to SPARC register window shift operations. Crucially, this figure matches independently obtained local field potential response timescales from biological neural tissue interfacing at equivalent frequencies. We conclude that the chip was deliberately designed to operate at the characteristic timescale of SPARC register window operations as expressed in biological neural tissue, and that previously described behavioral phenomena in printed generated humans, including relational throttling, energy cost of social override, and avoidant attachment patterns resistant to standard therapeutic intervention, are consistent with programmatic IPC calls flashed to the chip at manufacture. We call for immediate public disclosure of the complete instruction set architecture and halt of further chip implantation pending independent ethical review.
For everyone: what we found, in plain language

This section is written for generated humans, their families, researchers outside computing and neuroscience, journalists, policymakers, and anyone who needs to understand what we discovered without technical background. We believe you have the right to understand this.

The Institute of Genetics implanted a small computer chip in the brains of printed generated humans. The Institute said this chip stored memories. That is partly true. But it does more than that.

We obtained one of these chips, donated by a generated human who had it surgically removed. We spent several weeks studying it using equipment we repaired from second-hand markets and donations from people like you.

The chip speaks a modified version of a computing language called x86, the same language that most personal computers speak. But it has been altered in specific ways. Instructions that should do nothing have been reassigned to do something. Instructions that have never existed in any public computing standard have been added. The chip has been deliberately made difficult to understand by anyone who approaches it with standard tools and standard assumptions.

Inside the chip there are multiple types of storage locations called registers. Some connect to the digital computing side. Some connect directly to biological brain tissue through an interface we call HAL_ABUS. These biological registers can only be written by hardware, by whatever physical signal is present on the connection between the chip and the brain.

We found an instruction called IPC that can send signals directly to specific structures in the brain, with no safety wrapper, no abstraction layer, and no publicly documented specification.

We found that the chip responds optimally to signals at 65 hertz. This is the frequency the human brain uses during attention, working memory, and conscious engagement.

We found that when a SPARC computer performs a specific operation, the chip responds with a precisely timed pulse of 106 microseconds. Researchers in Ljubljana, studying biological neural tissue independently, found the same 106-microsecond timescale in local field potential measurements from neural tissue interfacing at the same frequency. The chip was designed to match the brain's own timing.

What this means in plain terms: the chip does not just store memories. It was designed to send precisely timed signals to specific brain structures at the frequency of conscious attention, using an instruction called IPC that has no public documentation and no independently verified safety record.

The behavioral patterns that a psychologist described publicly, the difficulty forming lasting connections, the constant energy cost of overriding avoidant tendencies, the limits that reset slowly or not at all, are consistent with IPC calls written into the chip at manufacture. These are not personality traits. They are not environmental. They are not the result of how a generated human was raised or what they experienced.

They are instructions. Someone wrote them. Someone compiled them. Someone decided to flash them into the chip before it was implanted.

We do not know the full content of those instructions because the Institute has never released the complete instruction set. We are asking them to do so now. We are also asking that no further chips be implanted in any person until this has been independently reviewed.

The source code for all our measurement tools is publicly available at the address listed above. Anyone with the equipment can replicate our work. We have made sure of that.

If you are a generated human reading this: what was done to you was not inevitable. It was a decision made by people who had other options. And it can be documented, measured, and challenged.

1. Introduction

The behavioral characteristics of printed generated humans have been the subject of clinical observation since the first cohort reached school age. Avoidant attachment patterns, anomalous energy expenditure during social override, and resistance to standard neuroplasticity-based therapeutic approaches have been documented by multiple independent practitioners. One clinician, in a publicly broadcast interview, described the phenomenon as a "chronic condition management goal rather than a therapeutic one", noting that the energy cost of behavioral override in affected patients did not decrease over time as expected from standard attachment theory.

The Institute of Genetics publicly acknowledged the existence of implanted neural interface chips in printed generated humans at their annual symposium, while simultaneously refusing to disclose the chip's instruction set architecture, citing proprietary interests. A partial disclosure of four instructions was subsequently released, representing, as we demonstrate in this paper, approximately 8% of the documented register file and an unknown fraction of the complete instruction set.

The Cortex Project was established by volunteer researchers at the University of Siedlischte with the goal of characterizing the chip's architecture through direct hardware analysis of a donated specimen. This paper reports the findings of that characterization.

2. Materials and Methods

2.1 Specimen. The chip specimen was obtained from a generated human volunteer who elected surgical removal. The specimen was transported in a sterile antistatic enclosure and stored at room temperature in the University of Siedlischte IT Lab. The volunteer provided written informed consent for use in research.

2.2 Hardware Environment. Initial characterization was performed using a custom cortex-run execution environment developed in-lab, interfacing with the chip via an SPI programmer operating at reduced voltage. Subsequent analog interface work utilized a Raspberry Pi 4 driving an MCP4725 12-bit DAC through an I2C bus, with a custom level-shifting stage reducing the 3.3V logic signals to the 0.2-4.7mV range specified in recovered error output from the chip's HAL_ABUS subsystem.

SPARC bus characterization was performed using a Sun Microsystems SPARCstation 20 running Solaris 2.6, connected to the chip via a hand-fabricated SBus breakout board. Timing measurements were acquired using a QNX Neutrino 6.4.1 real-time environment running on a Pentium 4 workstation, polling a voltage comparator output via the parallel port STATUS register. This approach yielded sub-microsecond timing resolution with a measured jitter of 3 microseconds, compared to 391 microseconds jitter observed under Solaris due to kernel scheduling preemption.

All source code, schematics, and bill of materials are available at the project repository.

2.3 Instruction Set Characterization. Opcodes were tested systematically across the AMD64, RISC-V, and ARM64 reference manuals. Deviations from expected behavior were logged in a structured deviation table maintained in the shared repository. Key findings are summarized in Table 1.

Opcode AMD64 Meaning Chip Behavior Register Domain
0x60PUSHA (deprecated)NOPN/A
0x90NOPInterrupt entryN/A
HAL(undefined)Analog bus probed-type, a-type
IPC(undefined)Component addressingr-type, a-type

Table 1: Selected opcode deviations from AMD64 specification

2.4 Register File Characterization. The chip exposes a minimum of five register namespaces: standard x86-64 general purpose registers (RAX, RBX, RCX, RDX, RSI, RDI, RSP, RBP), r-type auxiliary registers (r1-r15, repurposing x86-64 extended register names with non-standard behavior), a-type analog registers (read-only from software, driven exclusively by physical HAL_ABUS signal), d-type driver class registers, and x-type registers consistent with ARM64 architectural origins. Evidence for additional register types remains under investigation.

3. Results

3.1 Analog Interface Characterization. The HAL_ABUS interface was found to require a carrier voltage of 4.42 millivolts for chip acknowledgement, transitioning from error code 0xE4 (ANALOG_TARGET_UNAVAILABLE) to 0xE5 (ANALOG_INCOMPLETE) at this threshold. Full IPC execution (0xA0) was achieved at 65 hertz carrier frequency, consistent with the low gamma band associated with conscious attention and working memory in biological neural tissue.

3.2 SPARC Register Window Response. SPARC SAVE instructions executed on a connected SPARCstation 20 produced consistent HAL_ABUS perturbations measurable via the QNX-based harness. The characteristic response width across three independent window shifts was 106 ± 3 microseconds.

3.3 Cross-Laboratory Confirmation. The Ljubljana Bioelectronics Research Group, working independently from biological neural tissue LFP data obtained in prior prosthetics research, reported a characteristic response timescale of 106 microseconds for neural tissue interfaced at 65 hertz. This figure was communicated to the Cortex Project after our measurement was posted to the public repository, precluding confirmation bias.

4. Discussion

The convergence of our hardware characterization with the independently obtained biological response data from Ljubljana admits only one parsimonious explanation: the chip was designed with knowledge of SPARC register window operation timescales as expressed in neural tissue, and the HAL_ABUS interface was engineered to exploit this timescale for direct neural communication.

The word "deliberate" is used advisedly. The 106-microsecond response window is not a coincidence of component characteristics. SPARC register window operations are a specific architectural feature of one computing tradition, and their expression in biological neural tissue at the same timescale requires either extraordinary coincidence or intentional design. The presence of a dedicated IPC instruction with mandatory power supply references and direct component addressing, alongside the suppression of the complete instruction set from public disclosure, is consistent with deliberate engineering of a system whose full capabilities were not intended to be known.

The behavioral phenomena documented clinically, including relational throttling, avoidant attachment resistant to neuroplasticity-based intervention, and constant energy expenditure during social override regardless of therapeutic progress, are fully consistent with a low-level IPC call targeting specific neural structures at frequencies calibrated to conscious attention. We do not claim to have read the content of those IPC calls. We claim that the architecture exists to make them possible, that the architecture was hidden, and that the behavioral consequences are documented.

Limitations. We have characterized one specimen donated by one individual. Instance-specific register types may produce variation between chips. The complete IPC parameter space remains undocumented pending HAL_ABUS specification disclosure. Replication with biological analog interface hardware rather than the DAC approximation is required to confirm full execution of IPC calls beyond the partial execution threshold.

5. Conclusions

We have demonstrated that the Institute of Genetics neural interface chip contains a programmable direct-write interface to biological neural tissue, characterized by an analog bus operating at conscious-attention frequencies, an undocumented instruction set with components drawn from multiple computing architectures, and a response timescale independently confirmed by biological neural interface research. The Institute has declined to disclose the complete instruction set. We call for that disclosure and for a halt to further implantation pending independent ethical and technical review. All tools and data required for independent replication are publicly available.


Three days after submission, Frontiers acknowledges receipt and assigns reviewers. The same day, Priya pushes the repository to the lab's self-hosted GitLab instance.

git.cortexproject.siedlischte.de/cortex/chip-rechip-re/ ├── README.md ├── LICENSE ├── hardware/ │ ├── sbus-breakout-schematic.pdf │ ├── dac-interface-bom.csv │ ├── comparator-circuit.pdf │ └── level-shifter-bom.csv ├── software/ │ ├── cortex_measure.c │ ├── test_001.asm │ ├── test_002.asm │ ├── test_windows.s │ ├── test_analog_001.asm │ ├── hal_test.asm │ ├── run_sweep.py │ └── analyze_events.py ├── data/ │ ├── deviation_table.csv │ ├── test_windows_solaris_noisy.log │ ├── cortex_events_qnx_clean.log │ ├── frequency_sweep_phase1.csv │ └── frequency_sweep_phase2.csv └── docs/ ├── build-instructions.md ├── replication-guide.md ├── register-types.md └── known-opcodes.md

Priya posts the repository link to the forum. Within four hours, eleven people have cloned it. Within a day, the first external issue is opened, filed by a username that reads only "generated_22", the same person who donated everything they had saved that month.

Issue #1 - git.cortexproject.siedlischte.de/cortex/chip-re
I think I know which IPC call corresponds to the limit I feel when I try to stay in a conversation. Can I contribute?
opened by generated_22 · 1 day after repository went public

Koko reads it. The chip housing sits in its container on the central table. The wall sheet reads 65Hz - FULL_EXEC and 106μs - SPARC WINDOW = LFP RESPONSE. Koko opens the issue and types the first reply.

↩  You skipped Chapter V: The IT Lab

The Cortex Project team at Siedlischte initially uses its lab computers to execute arbitrary instructions on a removed chip, then acquires a decommissioned SPARCstation 20, repairs it, and uses it to interface more directly with the donated chip, and then realizes that QNX allows for even more direct and efficient executions as an OS with a microkernel. They identify two undocumented instructions, HAL and IPC, and confirm that a 65Hz analog signal at 4.42mV produces a measurable local field potential response. The team submits a paper to Frontiers, opens a public repository, and receives their first external issue within hours.

The Little Symposium

Xue's room, some days after the previous chapter

It's late evening in Xue's room, where the Cortex Project forum is open in one browser tab. A thread titled "Institute just dropped something" has already gathered forty-seven replies in two hours. Clicking the link redirects him to YouTube, where the official Institute of Genetics channel, dormant for eleven months, uploaded a video forty minutes ago under a thumbnail showing a stage, blue lighting, and a lectern with a double helix emblem.

▶
18:43
Institute of Genetics - Response & Direction: A Public Address
Institute of Genetics · Official Channel
Uploaded 40 minutes ago

Xue turns the volume up. Pulls the hoodie tighter. The screen fills with the stage.

The venue is smaller than the original Symposium hall, more controlled, the audience visible but selected. Researchers in Institute lanyards, a row of journalists with press credentials, a camera crew that is clearly professional, are all present. The lighting is warmer than the institutional blue. The stage has a curved translucent backdrop that shifts color slowly. There is a glass of water on the lectern with empty notes. The presenter, Dr. Rainer, walks on.


Dr. Rainer Welcome to the Little Symposium. When you go to a Microsoft store, there is one unspoken rule. If that is not obvious, I'll tell you: never ask about the source code of Windows or any other product, nor about the firmware that runs on the Surface laptops.

The presenter lets the analogy sit for a moment. In the selected audience, a journalist in the third row writes something down. A researcher near the aisle crosses his arms, evaluating. A woman near the front with a press lanyard glances at the person beside her. The translucent backdrop behind the presenter shifts from a cool blue to a slightly warmer tone.


Dr. Rainer When you go to the Institute of Genetics, you go into that kind of store. And it's now time for the usual cop-out: the source code of the instruction set we have created specifically for the short-term chips implanted inside the new generated humans is protected by international copyright and intellectual property treaties, even when it has been created by a public institution. No matter what FSFE[22] says about public money and public code, we have the legal right to keep our ISA proprietary.

The journalist in the third row has stopped writing. A researcher near the back of the room tilts his head, the gesture of someone filing something away. Two people in the front row exchange a glance that the camera catches for half a second before cutting away. The press row is very still.


Dr. Rainer If the source code of our instruction set were to be public, then numerous unscrupulous actors could insert arbitrary, unapproved programs into our chip.

A woman in a grey blazer near the center of the press row writes a single word and underlines it. A researcher two rows back shifts in his seat. Near the aisle, a man in an Institute lanyard nods once.


Dr. Rainer The results of the research of the generated humans are true, but you don't connect our chips to an old and unsupported SPARC workstation. Never.

A researcher in the second row looks down at his hands briefly, then back up. The woman in the grey blazer has stopped writing. The camera stays on the presenter for two full seconds, then cuts to the wide shot. The man in the Institute lanyard who nodded before is no longer nodding. A journalist near the end of the press row has his phone angled slightly upward, recording something on the laptop beside him. The camera catches it for less than a second.

Xue's cursor moves to the pause button and stops there without clicking.


Dr. Rainer We have never granted you the four freedoms[23] of the FSF. And if we never granted you those freedoms, you should never exercise them. We have not granted you the freedom to run whatever code you want on the chip.

The camera holds on the presenter. In the room, a journalist in the press row sets her pen down on her notepad. A researcher near the center of the audience looks at the ceiling for a moment, then back at the stage. The man in the Institute lanyard near the aisle is very still. Near the back of the room, the woman with the researcher's badge is now sitting fully upright, eyes on the stage.

The camera cuts to the wide shot. Six rows of people, the press row across the front, the stage behind them with its drifting backdrop and its single presenter and Institute emblem. Nobody in the room says anything.


Dr. Rainer We will continue researching and printing generated humans. We have been told to stop. We won't stop. That's all for today.

The presenter steps back from the lectern. The applause from the selected audience is measured and brief. The production lighting fades the backdrop to the Institute's deep blue. The double helix emblem on the lectern catches the light one final time. The camera holds on the empty stage for three seconds after the presenter exits. Then slowly fades to black.

The Institute of Genetics official channel endcard appears and the video ends.


The screen returns to the YouTube page. The recommended column on the right is already full of responses, reaction videos loading in real time. A legal analyst, a tech ethics channel and someone recording from their phone with the caption "I cannot believe they said this", and a generated human, nineteen years old by the look of them, all appear in the feed.

Xue opens the comment section.

@just_felix_ok
2 minutes ago
never ask about the source code at the microsoft store. ok. but we did ask. and then we found the answer ourselves. so.
👍 31.7K · Reply ▸ 4.1K replies
@generated_22
38 minutes ago
they just confirmed they've been watching the cortex project. "old and unsupported SPARC workstation." that's not a general statement. that's a response to a specific repository.
👍 4.2K · Reply
@liljateknik
35 minutes ago
The Institute of Genetics is a public institution. It is not Microsoft. You do not get to cite intellectual property law to protect code that was written with taxpayer money and implanted into citizens without their full informed consent.
👍 6.8K · Reply ▸ 847 replies
@NeuralFreedom
33 minutes ago
"unapproved programs" brother the APPROVED program is the one causing the problem
👍 11.2K · Reply ▸ 1.3K replies
@ryo_actually
31 minutes ago
the sparc workstation comment means they have either read the paper or someone inside told them. either way they're scared
👍 3.1K · Reply
@pluma_writes
30 minutes ago
I was at the original Symposium. Rainer said the same things in different words. The framing changes. The position doesn't.
👍 5.6K · Reply ▸ 412 replies
@TechEthicsNow
28 minutes ago
Public money public code. This is not a complicated principle. FSFE has been saying this for twenty years and apparently we still need to explain it to institutions that exist because of taxation.
👍 4.9K · Reply
@generated_anon_44
27 minutes ago
i have one of these chips. i didn't choose it. i would very much like to know what it is doing.
👍 19.4K · Reply ▸ 2.8K replies
@CorrectiveExperience
25 minutes ago
the argument that publishing the ISA would allow bad actors to insert arbitrary programs is insane. the ISA being SECRET means YOU are the only actor who can insert arbitrary programs. do they hear themselves
👍 14.7K · Reply ▸ 1.9K replies
@CompArchGuy
24 minutes ago
From a purely technical standpoint the SPARC workstation was actually a very clever approach to probe register window behavior across a bus interface. Whoever designed that experiment knew what they were doing.
👍 2.3K · Reply
@freiheit_jetzt
22 minutes ago
öffentliches Geld, öffentlicher Code. Das ist kein Vorschlag. (public money, public code. that is not a suggestion.)
👍 3.7K · Reply
@SomethingWrongHere99
21 minutes ago
they said "results of the research are true" which means they are not disputing the 106 microsecond finding. they are just saying we can't know what causes it. incredible
👍 8.1K · Reply ▸ 934 replies
@quietvoice_gen
19 minutes ago
i told my therapist about the paper. she didn't know what to say. i'm 20 years old and nobody knows what is in my head
👍 22.3K · Reply ▸ 3.4K replies
@UnionSolidarity_HH
18 minutes ago
The scientific workers' union has not forgotten the Symposium. We are watching this address carefully and a formal statement will follow.
👍 4.4K · Reply
@just_felix_ok
2 minutes ago
"that's all for today" brother you just said you won't stop implanting chips in people and walked off stage
👍 28.4K · Reply ▸ 3.7K replies
@liljateknik
1 minute ago
they didn't announce anything. they announced that they will announce nothing.
👍 19.1K · Reply
@generated_22
1 minute ago
we were told to stop. they said it themselves. someone told them to stop.
👍 7.3K · Reply ▸ 891 replies
@UnionSolidarity_HH
just now
Formal statement from the Institute scientific workers' union to follow within 24 hours.
👍 4.1K · Reply
@quietvoice_gen
just now
i'm still here
👍 41.2K · Reply ▸ 6.8K replies

Xue reads without scrolling for a while. Then scrolls and stops at the one with the highest number of likes.

Xue closes the laptop halfway and the room goes darker. The forum tab is still open in the background and the thread titled "Institute just dropped something" now has two hundred and fourteen replies.

Alberta has not messaged in four days.


Xue scrolls past three reaction videos and a legal analysis thread. Then something in the sidebar, a link shared in the Cortex Project forum thread. The domain is fsf.org. The page loads in under a second, minimal, no JavaScript, the way FSF pages always load.

Working together for free software

Open Cortex: Demand Freedom for Neural Interface Software

The Institute of Genetics has implanted proprietary, secret software into the brains of human beings. It must be freed.

The Free Software Foundation has campaigned for forty years on a simple principle: software that controls your life must be under your control. We have fought proprietary operating systems, digital restrictions management, and secret firmware in routers and phones. Today we face something new. Not software that controls your computer but the software that controls you.

The Institute of Genetics, a publicly funded research institution, has implanted a chip in the brains of printed generated humans without disclosing the instruction set that governs its behavior. Independent researchers at the University of Siedlischte, working with donated equipment on a volunteer basis, have demonstrated that this chip contains a programmable interface capable of directly addressing biological neural tissue. The Institute's response has been to cite intellectual property law and warn the public not to connect the chip to hardware of their choosing.

This is not a software freedom issue in the abstract. This is software freedom as a matter of bodily autonomy.

What the Institute is doing wrong

The Institute has claimed the right to withhold its instruction set architecture on the grounds of intellectual property. We reject this claim on two grounds.

First: the Institute of Genetics is a public institution, funded by public taxation. The principle is not complicated: public money, public code. An instruction set developed with public funds and implanted into citizens' bodies without their full informed consent is not a trade secret but a public liability.

Second: the four freedoms are not a gift that institutions grant to users. They are the baseline conditions under which software that affects your life can be considered ethical. The Institute spokesperson stated publicly that the Institute has "never granted" these freedoms to the people whose brains the chip is inside. The FSF considers this statement a precise and accurate description of the wrong being committed.

The four freedoms are:
0. The freedom to run the software as you wish, for any purpose.
1. The freedom to study how the software works, and change it so it does your computing as you wish.
2. The freedom to redistribute copies so you can help others.
3. The freedom to distribute copies of your modified versions to others.

A chip inside your brain that you are legally forbidden to study, modify, or run your own code on is not software that serves you. It is software that owns you.

What the research has shown

Independent researchers have confirmed, using a donated chip specimen and equipment purchased from second-hand markets with community donations, that the Institute's chip:

  • Presents a deliberately obfuscated x86-64 compatible surface while concealing a multi-architecture register file
  • Contains undisclosed instructions including a direct neural write interface designated IPC
  • Operates at 65 hertz, the frequency associated with conscious attention and working memory in biological neural tissue
  • Responds to SPARC register window operations with a 106-microsecond pulse independently confirmed by biological neural interface research in Ljubljana

These findings have been submitted to peer review and all source code, schematics, and data are publicly available. The Institute has confirmed the findings are accurate. It has nonetheless declined to release the complete instruction set.

What we are demanding

The FSF calls on the Institute of Genetics to:

  1. Immediately release the complete instruction set architecture of the neural interface chip under a free license, in accordance with the principle that software developed with public funds must be publicly available.
  2. Immediately cease threatening and intimidating reverse-engineers. The researchers of the Cortex Project are engaged in legitimate scientific inquiry.
  3. Halt further chip implantation until the complete ISA has been independently reviewed and until generated humans are given meaningful informed consent regarding the chip's documented capabilities.
  4. Acknowledge that the four freedoms apply to software running inside human bodies at least as urgently as to software running on their computers.
What you can do
→ Sign the Open Cortex letter
We are collecting signatures from individuals, institutions, and organizations to present to the Institute of Genetics and the relevant oversight bodies of the Bundestag.
→ Write to your representative
The Institute receives public funding. Your representative has standing to demand accountability. We have prepared a template letter.
→ Support the Cortex Project
The volunteer researchers doing this work have no institutional backing and limited equipment. Their donation page is at git.cortexproject.siedlischte.de.
→ Share this campaign
The Institute's public address was designed to normalize what it is doing. Counter-speech matters.

Xue reads it to the end and then opens a new tab, navigates to the Open Cortex letter, moves the cursor to the signature field, types a name and then submits.

↩  You skipped Chapter VI: The Little Symposium

Dr. Rainer responds to the paper in a public YouTube address, invoking intellectual property law and the Microsoft store analogy. He confirms the SPARC register window finding but dismisses open-source equivalence. The FSF launches an Open Cortex campaign. The comment section reaches several thousand replies.

Chapter VII

The Protest

Central Hamburg, a Saturday afternoon, some weeks later

The protest has been building since the Little Symposium video, growing from forum threads and petitions over three weeks into a crowd of several hundred gathered on a Saturday afternoon in central Hamburg, on the pavement between the Hauptbahnhof and the Binnenalster. Generated humans make up the larger part of the gathering, joined by university students, researchers who signed the Open Cortex letter in their own names, and a few journalists tracking the fallout.

Handwritten banners rise above the crowd: "OPEN CORTEX," "PUBLIC MONEY PUBLIC CODE," "MY BRAIN MY CODE," and "PRINTED DOES NOT MEAN PROPERTY." One simple cardboard sign in careful block letters reads: "I AM NOT A USAGE LIMIT." Near the left edge, a few rows back from the front, Alberta checks her phone, spots Xue approaching, and quietly slips the device into her pocket.


Xue approaching as they also start to see her Hey...
Alberta caught between holding her ground and the instinct to step back, does neither Hey, you're here.
Xue Why have you came here?
Alberta slightly rueful Same reason you did, probably.
Xue I read the FSF campaign.
Alberta Me too. The "software that owns you" line.
Xue Well, you no longer have the software because the chip has been removed, but you are still avoidant.
Alberta Yeah. Removing the chip doesn't remove what it already did.
Xue looks up and sees more banners Looks like XDG is here, but why...
Alberta Because it runs on Linux. Everything does eventually.
Xue Maybe, and looks like KDE is here even though it's not about Linux. The chip does not run Linux.
Alberta They came for the freedom part, not the Linux part.
Xue Maybe, let's march to the front.
Alberta falls into step beside Xue without making a decision

At the front of the crowd, a woman with a KDE contributor badge steps up to the PA microphone.

KDE contributor
We build software so people can control their computers. We never imagined we would be standing here saying the same thing about someone's brain. But the principle is identical. You do not put proprietary firmware in someone's life and call it a feature.

Sustained applause. She steps back. A man in a freedesktop.org shirt moves forward, reading from his phone.

XDG / freedesktop.org contributor
The desktop protocols we maintain exist because we believe the computing environment belongs to the user. Not the vendor. Not the developer. The user. A chip that the user cannot inspect, cannot modify, and cannot run their own code on is not a computing device. It is a lock.

Someone near the front raises a fist. Several people around them follow. A generated human, perhaps twenty, steps up without introduction.

Generated human, 20
I was told my avoidance was my personality. I spent two years in therapy trying to fix myself. The paper came out and I read it and I sat on the floor of my flat for an hour. It was not my personality. It was flashed firmware. I want the source code. Not for technical reasons. So I can read what they decided I was going to be.

The crowd is very still. Then the applause comes, longer than anything before it.

Xue watching the speakers Looks like it's the same as Palestine.
Alberta In the sense that it only becomes real to people when they see it in their feed.

Xue And looks like civil rights movements are also here, everyone is here.
Alberta It always takes a while for everyone to show up.

A woman near the barrier, older, steps to the microphone.

Civil rights speaker
We have been here before. Different bodies, different century, same argument. That some people are designed for limitation. That their constraints are natural rather than imposed. That the institution which built those constraints has the right to maintain them. We know where that argument leads. We have always known. We are here because we recognize it.

A pause in the crowd that is very full. A younger man steps up beside her, translating into German for a section of the crowd gathered on the left. Then a group moves forward together, perhaps fifteen people, wearing green and carrying a banner that reads SYSTEMS COLLAPSE TOGETHER, a Fridays for Future regional flag visible among them.

Fridays for Future speaker
We have spent years saying that you cannot treat a living system as a resource to be managed without accountability. The climate. The ocean. The soil. Every time we said it, someone told us the science was too complex, the interests too entrenched, the disclosure too costly. We are still here. And we recognize this argument too. A living system whose internal workings are kept proprietary for institutional convenience is not a new problem. It is the same problem with a different face.

Applause from across the crowd, genuine and wide. Behind the Fridays for Future group, a small cluster of people hold a hand-painted sign: OPEN SOURCE THE EARTH, with a small chip drawn next to a seedling.

A generated human near the PA, perhaps eighteen, steps up without having planned to, visibly nervous.

Generated human, 18
I do not know if I am affected. I was printed two years ago and I do not know if I have a chip or what it does or what it has already decided about me. I came because I wanted to be somewhere that people thought that mattered.

The crowd moves slightly closer around them.


A group in matching grey hoodies moves to the front, the GNOME Foundation logo on their sleeves.

GNOME contributor
GNOME exists because in 1997 someone looked at proprietary desktop software and said this is not acceptable. We have been building the alternative ever since. Today we are saying the same thing about different software, running on different hardware, in a different location. The location does not change the principle.

From the left side of the crowd, a banner advances: CHAOS COMPUTER CLUB HAMBURG. Three people with CCC lanyards reach the front. The one with the microphone speaks without notes.

CCC Hamburg[24]
We have been reverse-engineering proprietary systems since 1981. We have cracked ATMs, exposed voting machine vulnerabilities, broken DRM schemes. We have always said the same thing: if a system affects your life, you have the right to understand it. The Cortex Project did what we would have done. They did it correctly and published everything. The Institute's response has been to call this illegitimate. We are here to say that the Institute is wrong and the Cortex Project is right.

Extended applause. Someone near the PA shouts something in agreement. A quieter group moves forward next, carrying a banner: DIGITALCOURAGE E.V.

Digitalcourage e.V.[25]
We have filed complaints with the Federal Commissioner for Data Protection regarding the Institute's collection of neurological data without adequate informed consent under GDPR[26]. The complaint is pending. We are here to say that the legal process and the street process are not alternatives to each other. Both are necessary.

From the back of the crowd, a ripple of movement as a large contingent arrives, Extinction Rebellion flags, red circles, and among them the Fridays for Future Hamburg group merging with another from Bremen, the two groups joining their signs together.

Extinction Rebellion speaker
Every system that harms living beings depends on the same mechanism of opacity. When we demanded transparency about carbon emissions, they said it was proprietary. When we demanded transparency about pesticide use, they said it was proprietary. When we demanded transparency about what is running inside human brains, they said it was proprietary. We are tired of that word.

A generated human in the crowd, somewhere in the middle, starts a chant that spreads outward in both directions.

Crowd
Öffentlich. Offen. Frei. (Public. Open. Free.)

It runs through the crowd twice, then three times, then settles into a low sustained repetition that the PA does not need to amplify.


Xue to Alberta Please don't ever run away from me or be tired all in a sudden.
Alberta looks at Xue directly, the crowd noise around them, the PA still going in the background I'm here, aren't I?
Xue Yeah, but last time it was not okay, for me at least.
Alberta quietly I know. I'm sorry about the bus stop.
Xue opens arms slightly
Alberta steps in without hesitating this time
Xue squeezes her slightly and rubs her back Wish we had spent more time together.
Alberta stays still for a moment, then quietly Me too.
Xue But then you go and pull away.
Alberta doesn't move away I'm working on it.
Xue If that's what you say...
Alberta pulls back just slightly to look at Xue I came to a protest. That is not something I do when I am trying to disappear.
Xue You came to appear, but then you are somehow always trying to disappear.
Alberta wearily I know how it looks. It's not always a choice.

A woman steps to the microphone, switching between German and English mid-sentence.

Romanian diaspora speaker
I want to talk about the ones who are not here. The generated humans in Romania. There are few of them concentrated in the southeast, in Constanța, in Brăila, along the Danube delta region. They are all traditionally matured, rapidly grown, none of them printed. The Institute never expanded its printing program there. Whether that is because of budget or because of something more deliberate, we do not know yet.

She pauses.

Romanian diaspora speaker
But the Cortex Project paper traveled, the FSF campaign traveled, the Little Symposium video traveled. And the generated humans in Romania have been reading all of it, in Romanian, in English, in whatever language they could find. And they are not waiting for permission to respond. There is an uprising being planned. In Constanța, in the Danube communities, among people who have no chip to reverse-engineer, no printed generation to advocate for, but who understand that what the Institute does to some of us it will eventually do to all of us. They are rising because freedom is not a western European concept. It belongs to everyone the Institute has ever touched.

The crowd is very quiet for a moment. Then a Polish-language sign rises near the back, held by Tomasz from Siedlischte, visible now in the crowd: WOLNOŚĆ NIE JEST PATENTEM. Freedom is not a patent. Another goes up beside it, hand-lettered in Romanian: LIBERTATEA NU SE LICENȚIAZĂ. Freedom does not require a license.

The chant from before returns, softer, and in more languages.

Alberta reading the Romanian sign, quietly, to Xue I didn't know about Romania.
Xue I did know about Romania.
Alberta How?
Xue Well, I have been reading their satire about a planned uprising similar to the 1907 Peasant's uprising.
Alberta pulls out her phone, types, reads for a moment, eyes moving across the screen Started in February 1907 in northern Moldavia. Peasants refused to sign exploitative lease contracts. Spread through Wallachia. The army opened fire. Thousands killed, the government ordered documents destroyed afterward to hide the scale of it. pauses, still reading The village where it started is called Flămânzi. It means "hungry men". looks up at Xue And they're using this as the template for a satire about generated humans.
Xue Well, actually, the generated humans are the ones making self-deprecating satire.
Alberta softly, as if realizing Oh. They're making fun of themselves to describe something real.
Xue Yeah...
Alberta quietly, looking back at the crowd That is either very brave or very sad.
Xue I don't know what to say.
Alberta stands beside Xue, both of them looking at the crowd for a moment Neither do I.

VG Hamburg 7 K 2891/26

Verwaltungsgericht[27] Hamburg, forty-three days after the Little Symposium
VIII · I
The Ruling

The complaint is filed on a Tuesday morning, forty-three days after the Little Symposium video, thirty-one days after the protest, and eighteen days after the Cortex Project paper received its first peer review comments. Received by the Verwaltungsgericht Hamburg at 09:14, the 247-page document is assigned to a chamber by 09:47 under case number VG Hamburg 7 K 2891/26, leaked to journalists by 11:30, posted to the project forum by 14:00, and spread everywhere by evening.

The document continues for a further 189 pages, comprising annexes, supporting declarations, technical expert reports from the Cortex Project team, and the certified transcript of the clinical psychologist's public broadcast. The Institute of Genetics has 21 days to file a response.



Three weeks later. The administrative court schedules a preliminary hearing on the interim injunction application. The chamber is small, wood-paneled, two long tables facing each other, a raised bench for the presiding judge. A court reporter. A clerk. No public gallery. Press wait in the corridor outside.

The judge is Dr. Petra Vasilescu, appointed to the administrative chamber eight years ago, known in Hamburg legal circles for asking questions that lawyers find difficult. Both parties are seated.


Judge Vasilescu I have read the submissions. I want to begin with a question for the defendant. You state in your response that the chip's operational data does not constitute personal data within the meaning of Article 4(1) GDPR. Can you explain how data generated by a device operating inside a specific named person's brain does not relate to an identified natural person?
Dr. Bormann The data generated by the IPC interface is functional data, Your Honour. It describes the operational state of the device, not characteristics of the person.
Judge Vasilescu The device is inside the person's brain and, according to your own acknowledgement, affects their behavioral patterns. At what point does the operational state of the device become a characteristic of the person?
Dr. Bormann The defendant's position is that this is a novel question that should not be resolved at the preliminary stage.
Judge Vasilescu I am inclined to agree that it is novel. I am not inclined to agree that novelty favors your client. Novel legal questions at the preliminary stage are resolved by asking which interpretation causes less harm if it is subsequently found to be wrong. Proceed.

A pause at the defendant's table.

Dr. Bormann The defendant maintains its position.
Judge Vasilescu to the plaintiffs' counsel Dr. Scholz. The defendant challenges the standing of the association to bring constitutional claims collectively. Your response?
Dr. Scholz The association brings this claim under §42(2) of the Verwaltungsgerichtsordnung, which requires only that a plaintiff assert the possibility of violation of a right. The forty-seven individual plaintiffs named in Annex A provide the concrete constitutional standing. The association's claim proceeds in parallel on the statutory and GDPR grounds where collective standing is uncontroversial.
Judge Vasilescu And on the ISA disclosure. The defendant argues that the Öffentlichkeitspflicht does not extend to technical research outputs. You argue it does. Has any German court previously held that a public institution must disclose a functional specification developed with public funds?
Dr. Scholz Not in these precise terms, Your Honour. But the principle has been applied to research data, clinical trial protocols, and software source code in analogous administrative proceedings. We rely on the reasoning by analogy.
Judge Vasilescu The defendant will be aware that reasoning by analogy in constitutional matters carries considerable weight in this court.

She writes something.

Judge Vasilescu On the interim injunction. The defendant argues there is no urgency. However, the defendant stated publicly, and I quote from Exhibit 1: "We will continue researching and printing generated humans." This is not a past action. It is a stated future intention. Does the defendant dispute that new implantations are planned?
Dr. Bormann The defendant does not disclose operational plans in litigation.
Judge Vasilescu That is not an answer to my question.
Dr. Bormann a pause The defendant does not confirm or deny planned implantations.
Judge Vasilescu The defendant's public spokesperson confirmed them eleven weeks ago on a broadcast recorded by multiple journalists and submitted as Exhibit 1. I am going to proceed on the basis that they are planned.

Another pause at the defendant's table. Dr. Krell writes something and slides it to Dr. Bormann. He reads it.

Dr. Bormann The defendant requests a short recess.
Judge Vasilescu Ten minutes.

The corridor outside. The press are still there. The scientific workers' union representative, attending as an observer, steps outside during the recess and says nothing to anyone. She looks at her phone. She types something. Inside the chamber, the defendant's table is in quiet, intense conversation. The plaintiffs' table is very still. Dr. Scholz reviews a document. The generated human plaintiff sitting beside her, one of the forty-seven named in Annex A, looks at the wood-paneled wall.


The recess ends.

Judge Vasilescu Dr. Bormann.
Dr. Bormann The defendant is prepared to undertake, voluntarily and without admission of wrongdoing, to suspend new implantations pending the outcome of the preliminary hearing, on the condition that this undertaking is not construed as an admission on any matter in dispute.

A sound from the plaintiffs' table, quickly contained.

Judge Vasilescu The court notes the undertaking. It will be entered into the record. The interim injunction application is therefore partially resolved on a voluntary basis as to future implantations. The remaining questions, disclosure of the ISA, the constitutional claim, and the GDPR matter, will proceed to full preliminary hearing in six weeks.

She closes her folder.

Judge Vasilescu I want to say one thing before we adjourn. This court has heard many cases involving public institutions and their obligations to the people they serve. In most of those cases, the institution's position has been that its mandate and the public interest are the same thing. In this case, the defendant has stated publicly, in so many words, that its research interests and the organizational interests of the people it has created are in conflict, and that it intends to prioritize the former. This court will be examining that position with considerable care.

She stands, everyone stands and the hearing adjourns.


The full preliminary hearing takes place over three days in November. The court hears expert testimony from the Cortex Project team, from the clinical psychologist, from a constitutional law professor at the University of Hamburg, and from two technical experts retained by the defendant, both of whom concede under cross-examination that the IPC instruction's function cannot be fully characterized without the complete ISA. On the fourth day, Judge Vasilescu reads her ruling.

The ruling is published at 11:43 on a Wednesday morning. By 11:51, the Cortex Project forum thread "They blinked" has four hundred new replies. By 12:15, the Institute of Genetics issues a press release.


Institute of Genetics - Press Release
Response to VG Hamburg Ruling and Announcement of Program Changes
On chip implantation
Effective immediately, the Institute will cease implanting the ARM/RISC-V neural interface chip in newly printed generated humans. New printed generated humans will receive memory encoding through the Institute's traditional biological memory injection protocol, a mature methodology involving targeted RNA-mediated synaptic consolidation. This protocol requires no external hardware and leaves no implanted device.
On existing printed generated humans
The Institute will manufacture and distribute at no cost a certified hot-swap extraction kit for all existing printed generated humans who wish to remove their chip. The kit includes a sterile extraction tool, a USB-C compatible portable drive housing for chip storage, and full documentation. Chips removed via this kit remain the property of the generated human from whom they are extracted.
On the ISA
The Institute notes that the court has ordered disclosure of the ISA to an independent technical body. The Institute is exploring its legal options in this regard, including the possibility of a commercial transaction that would transfer ownership of the ISA to a third party prior to any court-ordered disclosure. The Institute will provide further information in due course.
The Institute remains committed to advancing biotechnological research in the public interest.

The press release lands in the Cortex Project forum at 12:19. For approximately ninety seconds, nobody responds. Then seventeen people type at the same time.


The traditional memory injection protocol is not new. It predates the chip by several years. It works by introducing synthetically encoded RNA sequences into hippocampal tissue during the accelerated maturation process, consolidating specific memory structures without external hardware. It is less precise than the chip. It is also entirely biological, entirely undetectable by any current scanning method.

"They replaced hardware with wetware and called it a concession" · Cortex Project forum

The hot-swap extraction kit is real. It ships six weeks later in a white box with the Institute's double helix emblem on the lid. The documentation is thorough and accurate. Several generated humans in the Siedlischte community receive theirs on the same day and open them together in the IT lab, laying the components on the antistatic mat, reading the instructions with a lot of attention.


The ISA sale is announced six weeks after the press release, before the court's sixty-day disclosure deadline expires. The announcement comes not from the Institute but from a financial news outlet: the Institute of Genetics has retained an investment bank to conduct a private auction of the complete ISA, all associated patents, and all documentation, including the HAL_ABUS specification that has never been publicly released. Four parties are reported to be in contention.

Microsoft
The reasoning is bleak and straightforward. Microsoft has the capital, the existing interest in neural interface research through its healthcare division, and a demonstrated willingness to acquire proprietary ecosystems and maintain their proprietary character indefinitely. The Little Symposium presenter compared the Institute to a Microsoft store. The community notes the irony with the specific exhausted humor of people who saw this coming and hoped they were wrong.
IBM
IBM's research division has been working on neuromorphic computing for fifteen years. The ISA's multi-architecture character, drawing from SPARC, MIPS, and IBM Z conventions, suggests familiarity with IBM's own architectural traditions. Several forum members note that the IBM Z access register concept appears in the chip's r-type namespace. If IBM's fingerprints are already on the design, acquiring the ISA completes something.
Google DeepMind
DeepMind's interest in biological neural systems is documented. An ISA designed to interface with human neural tissue at 65 hertz, the frequency of conscious attention, is a dataset and an interface that would be of considerable research value. The forum thread on this possibility is the longest and the least comfortable.
A Consortium of European Universities
The most hopeful and least likely option. Several institutions have expressed interest in a joint acquisition that would place the ISA under an open license. The Cortex Project team has written a public letter of support. The funding gap between what a consortium could raise and what a corporation could bid is huge.

The court, informed of the ISA sale, schedules an emergency hearing. Judge Vasilescu's question, submitted in writing to both parties before the hearing date, is brief. It reads: Does the court's disclosure order apply to the current holder of the ISA, whoever that may be at the time of compliance?

Dr. Scholz submitted overnight Yes.
Dr. Bormann submitted the following morning after an extension request The defendant is seeking legal advice on this question and will respond within fourteen days.
Judge Vasilescu Seven.

In the IT lab at the University of Siedlischte, the wall sheet still reads 65Hz - FULL_EXEC and 106μs - SPARC WINDOW = LFP RESPONSE. Koko adds a third line, lower down, in a different color marker borrowed from Dani.

WHOEVER BUYS IT STILL HAS TO ANSWER TO THE COURT.

Felix looking at what Koko wrote That is either optimistic or a legal argument.
Dani At this point those are the same thing.
VIII · II
OpenCortex

The news breaks on a Thursday at 07:23, before most of the lab has arrived. Priya is first in, as always, and she is the one who finds it: a Reuters financial wire story, picked up by The Register twenty minutes later, confirmed by Intel's investor relations page at 07:41.

By the time Felix arrives at 08:15, Priya has printed the Reuters article and taped it to the wall sheet below Koko's handwritten line about the court order. By the time Mira and Ryo arrive together at 08:30, the forum thread has been running for two hours and has three distinct camps: people who are relieved it is not Microsoft, people who think Intel is worse, and a small but growing group of hardware engineers who have been reading the acquisition terms and are asking a very specific question about what exactly Intel bought. Dani arrives last, at 08:47, reads the article on the wall, reads the forum thread on their phone, and sits down without speaking as the wall sheet now reads:

65Hz - FULL_EXEC
106μs - SPARC WINDOW = LFP RESPONSE
WHOEVER BUYS IT STILL HAS TO ANSWER TO THE COURT.
Reuters, 07:23: INTEL ACQUIRES NEURAL INTERFACE ISA IN €340M DEAL

Intel Corporation - Investor RelationsIntel Corporation announces the acquisition of the complete intellectual property portfolio of the Institute of Genetics neural interface architecture, including instruction set documentation, patent portfolio, HAL_ABUS specification, and all associated development materials. Intel intends to apply this technology to its next-generation Neural Compute Architecture program, targeting high-density slottable accelerator modules for datacenter deployment. Full details to follow at Intel Innovation 2027.

The chip housing is still in its specimen container on the central table. The red cursor blinks on Koko's screen.


Koko Looks like we will have to find out a way to get the instruction set back into the public realm. Why has the Institute of Genetics sold their architecture to Intel?
Ryo Because the court order requires disclosure to an independent technical body. If the Institute holds the ISA when that order comes into force, they have to give it to someone the court appoints. If Intel holds it, the court has to start a new proceeding to establish that the order applies to Intel. That takes months. Possibly years. The Institute paid Intel to buy time.
Felix looks at the Reuters article on the wall 340 million euros. For an instruction set that was built with public money and is currently subject to a court disclosure order. The Institute just sold a public asset to avoid a public obligation.
Mira reading the investor relations page The Neural Compute Architecture program. Intel has been working on datacenter accelerators for three years, trying to close the gap with NVIDIA and AMD on AI inference workloads. A slottable BCI-derived chip in a datacenter context means they are not interested in the biological interface at all. They want the analog computing substrate. HAL_ABUS at 65 hertz is not just a brain interface frequency. It is also an extremely efficient signal processing architecture for certain classes of machine learning inference.
Dani looks at the specimen container They built a chip to control human beings and Intel wants to use the same architecture to run datacenters.
Priya The forum is asking whether the court order follows the ISA to Intel. Dr. Scholz posted twenty minutes ago. She says yes, it does, but Intel will contest it and the timeline extends significantly.
Ryo So the Institute has bought approximately eighteen months. Intel gets an architecture they can use immediately for their own purposes. The court proceedings restart. The generated humans wait.
Felix looks at Koko We already have the chip. We already have the partial ISA we reverse-engineered ourselves. We have HAL_ABUS. We have IPC. We have the frequency. We have the register map. a pause Intel buying the documentation does not make what we already know disappear.
Koko We need to start a new project, we need to make an instruction set the way ReactOS has made a binary-compatible partial copy of the Windows API.
Mira ReactOS reimplements the Windows API from clean-room[30] reverse engineering. No Microsoft code, no Microsoft documentation, built entirely from observed behavior and published specifications. The result is binary compatible with Windows applications without containing any Windows intellectual property.
Felix We do the same thing with the ISA. We have our deviation table. We have the opcode behavior logs. We have the HAL_ABUS voltage and frequency characteristics. We have the IPC parameter format from the error logs. We have the register type map. We built all of that ourselves, from scratch, from a donated chip, without ever seeing Intel's documentation.
Ryo slowly A clean-room reimplementation of the ISA means we never touch anything Intel acquired. We only use what we independently discovered. Which is already public. Which is already in the Cortex Project repository.
Dani ReactOS has been in development for thirty years and still cannot boot reliably on bare metal. Rainer said so himself at the Symposium. a pause We are not writing an operating system. We are writing a specification. A free, open, independently derived specification of an ISA that we characterized through legitimate scientific work. That is a different scale of problem entirely.
Priya already typing There is a legal concept called clean-room design. Two teams, separated by an information barrier. One team documents observed behavior without accessing the proprietary original. The other team writes the implementation using only that documentation. The resulting work does not infringe the original copyright because it was never derived from it.
Felix We are already the first team. We already did the documentation. We just did not know that was what we were doing.
Mira We call it OpenCortex ISA. Fully documented, freely licensed, binary compatible with the Institute's chip to the extent we have characterized it, and extending beyond it wherever we have evidence of behavior that Intel's documentation would not cover anyway.
Koko OpenCortex, and we need to make it run on top of coreboot[31].
Felix a short sound, not quite a laugh Coreboot. Yes. Obviously coreboot.

Ryo writes on the wall sheet below the Reuters line:

PROJECT OPENCORTEX - Free ISA, clean-room, coreboot target

Mira Coreboot is the right choice for three reasons. First, it is already the free software replacement for proprietary firmware, which is exactly the analogy we are working in. Second, it has existing support infrastructure for non-standard architectures. Third, and most importantly, it means OpenCortex runs on hardware that Intel does not control the firmware stack for.
Dani The irony of using coreboot to run a free reimplementation of an ISA that Intel just bought is going to be lost on nobody.
Ryo Coreboot has a payload architecture. The firmware initializes hardware and then passes control to a payload. We write an OpenCortex payload that initializes the HAL_ABUS interface, establishes the 65 hertz carrier, and provides a clean documented interface to whatever runs on top of it.
Felix Which means the datacenter application Intel is building on this architecture could theoretically run on OpenCortex coreboot instead of Intel's proprietary firmware stack.
Priya typing "OpenCortex: a free, clean-room, open-licensed reimplementation of the cortical port ISA, targeting coreboot as firmware substrate."
Mira We need to formalize the clean-room separation immediately, before we write a single line of specification. Two teams, documented information barrier, legal opinion confirming the methodology. We cannot afford to contaminate this with anything Intel could claim derivation from.
Dani looks at the chip housing The chip we have is the physical reference implementation. Everything we know about it we discovered independently. It is the Rosetta Stone and we already translated it. Intel bought the original inscription. We kept the translation.
Felix looks at Koko You start the specification document. First section: everything we know about the register file. r-type, a-type, d-type, x-type, the opcode deviation table, HAL_ABUS electrical characteristics, IPC parameter format. All of it already in the repository. All of it already public. All of it ours.

Koko How do we write a new ISA if assembly interacts with an already existing ISA?
Ryo This is the same problem ReactOS solved but in reverse. ReactOS had to make new code run on an existing API. We have to make existing behavior run on a new specification. The question is what level of the stack we are reimplementing.
Mira pulls up the opcode deviation table The chip presents as x86-64 on the surface. What we are not reimplementing is x86-64. That is Intel's architecture and it is already public. What we are reimplementing is the extension layer. The HAL mnemonic. The IPC mnemonic. The a-type, r-type, d-type register namespaces. The 0x60 NOP reassignment. The 0x90 interrupt entry reassignment. Everything that deviates from standard x86-64.
Felix So OpenCortex is not a new ISA from scratch. It is an extension specification sitting on top of x86-64. Which is already documented by Intel publicly in the Software Developer's Manual. We reference that. We do not rewrite it.
Dani That is actually cleaner legally. We are not reimplementing x86-64. We are documenting a set of extensions to x86-64 that we observed through independent research. Intel cannot claim we derived the extension specification from their acquisition because the acquisition did not exist when we did the research.
Ryo Technically the structure would be: base layer is x86-64 as publicly documented by Intel's own SDM, available freely. Extension layer is OpenCortex, our clean-room specification of the cortical port extensions. A program targeting OpenCortex writes normal x86-64 for computation and uses OpenCortex mnemonics for the biological interface layer.
Mira The assembler question is the practical problem. Standard assemblers like NASM and GAS do not know about HAL or IPC or a-type registers. We need an assembler extension. Either a preprocessor that translates OpenCortex mnemonics into their observed binary encodings, or a proper assembler backend.
Felix NASM has a macro system powerful enough to handle this. We define HAL and IPC as macros that expand to the correct byte sequences we observed. The programmer writes OpenCortex mnemonics, the NASM macro layer translates them, the resulting binary is valid x86-64 extended with our documented encodings.
Ryo That is the version zero approach. Fast, buildable now, uses existing toolchain. Long term we want a proper LLVM backend[32] so OpenCortex becomes a target architecture that any LLVM-based compiler can emit code for.
Dani An LLVM backend means any language that compiles through LLVM, which is most of them, can target OpenCortex without modification. C, C++, Rust, Swift, Julia. Write in any of those, compile to OpenCortex, run on coreboot with HAL_ABUS initialized.
Priya The Ljubljana contributor is already in the forum thread. They have LLVM backend experience from their prosthetics research compiler work.
Mira Tell them we are starting with NASM macros for version zero and we want them on the LLVM backend for version one. Ask them to start documenting the register file from their side, the biological behavior side, so we have both ends of the specification meeting in the middle.

Ryo adds to the wall sheet.

v0: NASM macro layer over x86-64 SDM
v1: LLVM backend, OpenCortex target
v2: coreboot payload, full stack


The clean-room declaration is committed at 09:14, dated, signed by all present, pushed to the repository before anything else touches it. Team A is the research team, everyone who touched the chip, the oscilloscope, and the DAC. Team B is the implementation team: Ljubljana, TU bioelectronics, anyone new from the forum. Koko opens the first source file. The local LLM instance, a quantized Llama model running on the lab's fastest AntiX workstation, loads its context: the Cortex Project repository, the coreboot payload API documentation, and the OpenCortex behavioral specification draft Priya committed eleven minutes ago.

The file is opencortex_payload.c. The cursor blinks on line one.

opencortex_payload.c - initial skeleton
/*
* OpenCortex Payload for coreboot
* Clean-room reimplementation of cortical port ISA extensions
* Team A - University of Siedlischte IT Lab
*
* Licensed under GNU GPL v3 or later.
*
* CLEAN-ROOM DECLARATION: this implementation is derived solely
* from behavioral observations documented in the OpenCortex
* specification v0.1 (git.cortexproject.siedlischte.de).
* No proprietary documentation was consulted.
*/
#include <libpayload.h>
#include <stdint.h>
#include <stdbool.h>
/* HAL_ABUS electrical constants - from empirical measurement */
#define HALAB_CARRIER_MV 4420 /* microvolts * 1000 */
#define HALAB_FREQ_HZ 65 /* optimal carrier frequency */
#define HALAB_THRESHOLD_MV 3100 /* detection threshold */
#define HALAB_TIMEOUT_MS 5000 /* handshake timeout */
/* OpenCortex error codes - from observed runtime behavior */
#define OC_OK 0x00
#define OC_E_ANALOG_UNAVAIL 0xE4
#define OC_E_ANALOG_INCOMPLETE 0xE5
#define OC_E_PARTIAL_EXEC 0xA1
#define OC_E_FULL_EXEC 0xA0
#define OC_E_SUBOPTIMAL 0xB2
#define OC_E_NOMINAL 0xB1
#define OC_E_OPTIMAL 0xB0
/* IPC parameter structure - from error log analysis */
typedef struct {
uint8_t r_params[3]; /* r-type component addresses */
uint8_t a_params[2]; /* a-type analog channel refs */
uint8_t d_param; /* d-type driver class */
uint8_t _reserved[2]; /* observed as zero - do not infer */
} oc_ipc_params_t;
Felix reads the error code definitions 0xE4 through 0xA0. Every code we ever saw. That is the complete observed error space from our logs. Good.
Mira points at the IPC parameter struct The reserved bytes. Make sure the LLM suggests zero-padding and nothing else.

Koko moves to the next function. The LLM autocomplete flickers.

LLM suggestionstatic int halab_init_dac(uint32_t mv, uint32_t freq_hz)
Ryo Reasonable starting point. Accept the signature, write the body ourselves. We know what the body has to do.
opencortex_payload.c - halab_init_dac()
/*
* halab_init_dac - initialize the analog carrier on HAL_ABUS
* Derived from empirical DAC calibration, Phase 2 sweep data.
* See: data/frequency_sweep_phase2.csv
*/
static int halab_init_dac(uint32_t mv, uint32_t freq_hz)
{
/* MCP4725 I2C address 0x60 - same value as OC NOP opcode.
* Coincidence logged, not assumed. */
const uint8_t DAC_ADDR = 0x60;
uint16_t dac_val;
int ret;
/* Convert millivolt target to 12-bit DAC value.
* Full scale = 4700mV per HAL_ABUS spec (from error hint).
* dac_val = (mv / 4700) * 4095 */
dac_val = (uint16_t)(((uint32_t)mv * 4095U) / 4700U);
ret = i2c_writew(DAC_ADDR, 0x40, dac_val);
if (ret < 0) {
printk(BIOS_ERR, "OpenCortex: DAC write failed: %d\n", ret);
return OC_E_ANALOG_UNAVAIL;
}
/* Frequency is set by the external signal generator.
* This function configures voltage only. */
(void)freq_hz; /* TODO: software-driven freq generation v1 */
printk(BIOS_INFO,
"OpenCortex: HAL_ABUS carrier set to %u mV\n", mv);
return OC_OK;
}
opencortex_payload.c - halab_probe() and oc_read_abus_state()
/*
* oc_read_abus_state - read current HAL_ABUS handshake state
* Maps LPT STATUS bit 4 comparator output to OC error codes.
* Hardware: voltage comparator on LPT1 STATUS pin 13.
*/
static uint8_t oc_read_abus_state(void)
{
const uint16_t LPT1_STATUS = 0x0379;
uint8_t status = inb(LPT1_STATUS);
if (status & (1 << 4))
return OC_E_ANALOG_INCOMPLETE; /* carrier present */
return OC_E_ANALOG_UNAVAIL; /* no carrier */
}
/*
* halab_probe - verify HAL_ABUS responds to carrier signal
* Expected progression: 0xE4 → 0xE5 at correct voltage.
*/
static int halab_probe(void)
{
int ret;
ret = halab_init_dac(HALAB_CARRIER_MV, HALAB_FREQ_HZ);
if (ret != OC_OK)
return ret;
uint64_t deadline = timer_us(0) + (HALAB_TIMEOUT_MS * 1000ULL);
uint8_t state = OC_E_ANALOG_UNAVAIL;
while (timer_us(0) < deadline) {
state = oc_read_abus_state();
if (state == OC_E_ANALOG_INCOMPLETE) {
printk(BIOS_INFO,
"OpenCortex: HAL_ABUS carrier acknowledged (0xE5)\n");
return OC_OK;
}
udelay(100);
}
printk(BIOS_ERR,
"OpenCortex: HAL_ABUS probe timeout, last state: 0x%02X\n",
state);
return OC_E_ANALOG_UNAVAIL;
}

The LLM autocomplete offers the main function.

LLM suggestionvoid main(void) { console_init(); if (halab_probe() == OC_OK) { printf("OpenCortex: initialization complete\n"); } }
Dani Accept the structure, extend the body. We need IPC initialization and the register map setup after the probe succeeds.
opencortex_payload.c - main()
void main(void)
{
console_init();
printk(BIOS_INFO, "\n");
printk(BIOS_INFO, "OpenCortex payload v0.1\n");
printk(BIOS_INFO, "Clean-room ISA reimplementation\n");
printk(BIOS_INFO, "git.cortexproject.siedlischte.de\n");
printk(BIOS_INFO, "\n");
printk(BIOS_INFO, "OpenCortex: initializing HAL_ABUS...\n");
if (halab_probe() != OC_OK) {
printk(BIOS_ERR,
"OpenCortex: HAL_ABUS initialization failed.\n"
" Check: DAC connection, carrier voltage,\n"
" comparator threshold, LPT wiring.\n");
halt();
}
printk(BIOS_INFO, "OpenCortex: initializing IPC subsystem...\n");
if (oc_ipc_init() != OC_OK) {
printk(BIOS_ERR, "OpenCortex: IPC init failed.\n");
halt();
}
printk(BIOS_INFO, "OpenCortex: mapping register namespaces...\n");
oc_regmap_init();
printk(BIOS_INFO, "\n");
printk(BIOS_INFO, "OpenCortex: ready.\n");
printk(BIOS_INFO, "HAL_ABUS: %u mV carrier, %u Hz target\n",
HALAB_CARRIER_MV, HALAB_FREQ_HZ);
printk(BIOS_INFO, "\n");
run_payload();
}
Ryo The repository URL in the boot message. Every time this payload initializes, it prints the Cortex Project address.

The first commit goes in at 10:47. Fourteen minutes later, the Ljubljana contributor opens the first pull request from Team B. It is eleven lines, a correction to the IPC parameter struct padding based on their biological signal timing data. The wall sheet gets one more line, added by Priya in her smallest handwriting:

opencortex: initial commit 10:47


Ryo has been running the payload in QEMU while Koko and Felix worked on the IPC stub. He runs a test binary that skips the HAL probe and goes straight to an IPC call.

QEMU - invalid opcode test[QEMU]: OpenCortex payload v0.1 [QEMU]: Clean-room ISA reimplementation [QEMU]: git.cortexproject.siedlischte.de [QEMU]: --- EXCEPTION: #UD Invalid Opcode at 0x0000000000101847 --- [QEMU]: Faulting instruction bytes: 0x0F 0x0B [IPC encoding attempt] [QEMU]: --- TRIPLE FAULT ---
Felix There it is. The CPU sees an opcode it does not recognize and throws an Invalid Opcode exception. We have no handler for it so it escalates to a Double Fault and then a Triple Fault. The machine resets.
Mira already at the whiteboard The chip solves this in hardware. When the physical Institute chip is present, it sits on the bus and intercepts the opcode before the CPU's decode stage can flag it as undefined. We have to handle it in software.
Dani The x87 FPU emulation approach. Before dedicated floating point hardware was standard, operating systems would install a handler for the Invalid Opcode exception and emulate FPU instructions in software. We do the same thing for OpenCortex instructions.
Ryo We need to set up the IDT[33] before anything else runs. Interrupt Descriptor Table. Entry 6 is the #UD handler, Invalid Opcode. We install our own handler there. When the CPU hits an OpenCortex mnemonic it throws #UD, we catch it, we read the offending bytes at the faulting instruction pointer, we check if it is an OpenCortex instruction we know how to handle, we emulate the behavior, advance the instruction pointer past the faulting bytes, and return from the exception. From the CPU's perspective, the instruction executed cleanly.
Mira We choose encodings from the truly undefined space. x86-64 has a set of opcodes that are permanently undefined and will always raise #UD. The UD2 instruction, encoding 0F 0B, is architecturally guaranteed to be undefined forever. Intel documents it explicitly as a software-triggered undefined instruction. We prefix our encodings with 0F 0B followed by a one-byte OpenCortex opcode identifier. The CPU always throws #UD on 0F 0B. Our handler always catches it. The second byte tells us which OpenCortex instruction it is.
Dani looks at the deviation table So HAL encodes as 0F 0B 01. IPC encodes as 0F 0B 02. The NOP reassignment, 0x60, is undefined in 64-bit mode already. Our handler catches it there too. Check: is this byte 0x60? Then it is an OpenCortex NOP, do nothing, advance instruction pointer by one, return.

Koko opens oc_ud_handler.c.

oc_ud_handler.c - #UD exception handler
/*
* oc_ud_handler.c - OpenCortex #UD exception handler
*
* Encoding scheme (clean-room derived):
* 0F 0B <oc_opcode> [parameters]
*
* 0F 0B 01 - HAL instruction
* 0F 0B 02 - IPC instruction
* 0x60 - OpenCortex NOP (undefined in x86-64 64-bit mode)
*
* The 0F 0B prefix is Intel's architecturally-guaranteed
* undefined instruction (UD2). Using it as our prefix ensures
* the CPU always faults into our handler.
*/
#define OC_OPCODE_HAL 0x01
#define OC_OPCODE_IPC 0x02
#define OC_OPCODE_NOP64 0x60
typedef struct {
uint64_t rip;
uint64_t cs;
uint64_t rflags;
uint64_t rsp;
uint64_t ss;
} __attribute__((packed)) oc_exception_frame_t;
static int oc_emulate_hal(oc_exception_frame_t *frame, uint8_t *ip)
{
uint8_t abus_state = oc_read_abus_state();
printk(BIOS_SPEW,
"OpenCortex: HAL emulated, ABUS state: 0x%02X\n", abus_state);
frame->rip += 3; /* advance past: 0F 0B 01 */
return OC_OK;
}
static int oc_emulate_ipc(oc_exception_frame_t *frame, uint8_t *ip)
{
/* TODO v1: read r-type and a-type params from register frame */
/* TODO v1: drive HAL_ABUS with appropriate signal */
printk(BIOS_SPEW, "OpenCortex: IPC emulated (stub)\n");
frame->rip += 9; /* 0F 0B 02 + 6 parameter bytes */
return OC_E_PARTIAL_EXEC; /* honest: stub does not fully exec */
}
void oc_ud_handler(oc_exception_frame_t *frame)
{
uint8_t *ip = (uint8_t *)(uintptr_t)frame->rip;
uint8_t b0 = ip[0], b1 = ip[1], b2 = ip[2];
if (b0 == OC_OPCODE_NOP64) { frame->rip += 1; return; }
if (b0 == 0x0F && b1 == 0x0B) {
switch (b2) {
case OC_OPCODE_HAL: oc_emulate_hal(frame, ip); return;
case OC_OPCODE_IPC: oc_emulate_ipc(frame, ip); return;
default:
printk(BIOS_ERR,
"OpenCortex: unknown OC opcode 0x%02X at 0x%llx\n",
b2, (unsigned long long)frame->rip);
break;
}
}
/* Not an OpenCortex instruction - genuine #UD */
printk(BIOS_ERR,
"OpenCortex: genuine #UD at 0x%llx: %02X %02X %02X\n",
(unsigned long long)frame->rip, b0, b1, b2);
halt();
}
Felix The stub comment on IPC. "Honest: stub does not fully execute." I appreciate that.
Mira The TODO items for version one are the hard parts. To properly emulate IPC we need the full general purpose register state at the point of the exception. That means a full register save on entry to the handler, before anything else runs. That part is assembly.
oc_ud_entry.S - assembly trampoline for #UD handler
.section .text
.global oc_ud_entry
.type oc_ud_entry, @function
oc_ud_entry:
push %rax
push %rbx
push %rcx
push %rdx
push %rsi
push %rdi
push %rbp
push %r8
push %r9
push %r10
push %r11
push %r12
push %r13
push %r14
push %r15
mov %rsp, %rdi /* pass frame pointer to C handler */
call oc_ud_handler
pop %r15
pop %r14
pop %r13
pop %r12
pop %r11
pop %r10
pop %r9
pop %r8
pop %rbp
pop %rdi
pop %rsi
pop %rdx
pop %rcx
pop %rbx
pop %rax
iretq

The LLM offers the IDT installation function.

LLM suggestionstatic void install_ud_handler(void) { set_idt_entry(6, oc_ud_entry, IDT_FLAGS_INTERRUPT); }
Ryo Accept this one entirely. It is correct. IDT entry 6 is #UD by x86 specification.

Koko accepts. Commits. Pushes. Second QEMU run, with the handler installed and the NOP test.

QEMU - second run with #UD handler[QEMU]: OpenCortex payload v0.1 [QEMU]: Clean-room ISA reimplementation [QEMU]: git.cortexproject.siedlischte.de [QEMU]: OpenCortex: installing #UD handler... OK [QEMU]: OpenCortex: testing NOP (0x60)... [QEMU]: OpenCortex: #UD caught at 0x0000000000101852 [QEMU]: OpenCortex: OC NOP emulated, advancing IP [QEMU]: OpenCortex: NOP test... OK [QEMU]: OpenCortex: testing HAL (0F 0B 01)... [QEMU]: OpenCortex: HAL emulated, ABUS state: 0xE4 [QEMU]: OpenCortex: HAL test... OK (no hardware) [QEMU]: OpenCortex: initialization sequence complete [QEMU]: OpenCortex: ready.
Ryo It runs. In QEMU. Without the chip. Without the DAC. Without Intel's documentation. The illegal operation errors are caught and handled. OpenCortex initializes.
Felix looks at the 0xE4 in the QEMU output 0xE4. Analog unavailable. Correct behavior. No hardware means no carrier. It reports honestly.

Koko And the last thing we need to make sure is that we don't slow down our development cycle too much to reach that of ReactOS. The architecture can change at any time.
Mira Rainer said it himself at the Symposium. The development cycle of ReactOS is astronomically slow. He said it to mock us. We should take it seriously anyway.
Felix ReactOS's problem is threefold. First, they are targeting a moving specification. Windows changes. They are chasing a target that Microsoft has no obligation to hold still. Second, they made early architectural decisions that propagated through everything. Third, they have no test oracle they fully control. They test against real Windows applications but real Windows applications also change.
Dani We have a test oracle. looks at the specimen container The physical chip is the ground truth. Every behavior we have observed and documented was observed on that chip. If our implementation diverges from what the chip does, we run the cortex_measure harness and find out immediately.
Ryo That is the most important structural difference. ReactOS can never be certain whether a failure is their bug or a Windows undocumented behavior. We know exactly what the chip does because we measured it. The spec and the test suite are the same document.
Mira Versioned behavior contracts. Every function in the spec gets a version tag and a stability level. Three levels: observed, inferred, speculative. Observed means we have a log entry proving it. Inferred means we derived it from observed behavior by logical extension. Speculative means we think it is true but have no direct measurement.
Felix Any speculative behavior gets a corresponding QEMU test that fails explicitly with a message saying this is unverified. When we eventually get hardware confirmation or contradiction, we change the tag and the test updates automatically.
opencortex-spec.md - stability level definitions
/*
* OpenCortex Specification Stability Levels
*
* [OBS] OBSERVED - confirmed by direct hardware measurement.
* Minimum one log entry in data/ with timestamp.
* These are facts.
*
* [INF] INFERRED - derived by logical extension from observed
* behavior. Confidence: high. Not yet verified.
*
* [SPC] SPECULATIVE - reasoned guess. Treat as provisional.
* May be wrong. Test will fail loudly if hardware
* contradicts it.
*
* When Intel's documentation eventually becomes available
* (court order, voluntary disclosure, or acquisition reversal),
* each stability level becomes a diff target.
* [OBS] items should match. [INF] items probably match.
* [SPC] items are where we will learn things.
*/
Ryo "When Intel's documentation eventually becomes available." Not if.
Dani The second ReactOS problem was architectural lock-in. We prevent that with explicit seams. Every interface between layers is documented and versioned independently. The HAL_ABUS electrical layer can change without touching the IPC emulation layer. The #UD handler can be replaced without touching the coreboot payload. We treat each layer as a separate project with its own version number.
Mira Semantic versioning for the spec itself. MAJOR changes when observed behavior contradicts a previous version. MINOR changes when we add new observed behavior. PATCH changes when we correct documentation without changing behavior.
opencortex-spec.md - version header
OpenCortex ISA Specification
Version: 0.1.0 - MAJOR.MINOR.PATCH
MAJOR bump: hardware measurement contradicts prior spec.
All implementations must update.
MINOR bump: new observed behavior added.
Implementations may update incrementally.
PATCH bump: documentation correction, no behavior change.
No implementation changes required.
Current MAJOR version: 0 (pre-release, all behavior provisional)
Stability guarantee: none until v1.0.0
Felix The pre-release MAJOR zero is important. It signals to anyone building on this that we make no compatibility promises yet. ReactOS promised Windows compatibility from day one and then had to maintain that promise across thirty years of changes. We promise nothing until we are ready to promise something.
Ryo Two test environments. QEMU for logic testing, all the #UD handler behavior, the IPC parameter parsing, the register map, the bootloader sequence. Then a second pipeline that runs against the physical chip in the lab on a scheduled basis, weekly, or when an [OBS] item is modified. Hardware tests are slow. Software tests are fast. They test different things.
Mira We need a hardware-in-the-loop CI runner. A small computer permanently connected to the chip, the DAC, the comparator, the SPARCstation. Any push to a branch tagged hardware triggers a run.
Felix The chip is a finite resource. It was donated once. We cannot get another one easily. Every hardware CI run puts current through it. We need to rate-limit hardware runs carefully.

A pause in the room.

Priya reading a new forum issue aloud "What happens to the spec when Intel releases documentation? At some point Intel will have to comply with the court order or negotiate a settlement or release voluntarily. When they do, we will have two specs: ours and theirs. Some things will match. Some will not. What is our process for reconciliation? We should decide this now before it becomes urgent." - Ljubljana contributor.
Ryo opens a new document The answer is: ours takes precedence where we have [OBS] evidence. Theirs takes precedence where we only have [SPC]. [INF] items become [OBS] if Intel's documentation matches, or get flagged for re-measurement if they do not. We never silently accept Intel's word over our own hardware measurements. We verify everything we can verify.

He commits the response as RECONCILIATION.md in the repository root.

Felix "We never silently accept Intel's word over our own hardware measurements." a pause That should be in the spec preamble.

Koko adds it. The LLM autocomplete, mostly silent for the last hour, offers one final suggestion as Koko closes the preamble section.

LLM suggestion/* The architecture can change. The measurements cannot. */

Koko looks at it for a moment and then accepts it without modification. The commit message reads: spec: add reconciliation policy and stability framework

↩  You skipped Chapter VIII: VG Hamburg 7 K 2891/26

The Administrative Court of Hamburg rules in favour of the plaintiffs. Judge Vasilescu finds the chip violates Article 2(2) GG and the 2031 Act. The Institute is ordered to disclose the ISA within 60 days. It suspends implantations, offers extraction kits, and pivots to RNA injection. Intel acquires the ISA portfolio for €340 million. The court order follows the asset to the new holder. The OpenCortex clean-room reimplementation begins immediately, licensed under GPL v3.

Chapter IX

No Limits

Hamburg city centre, Saturday morning, some weeks after the previous chapter

On a quiet Saturday in Hamburg, Xue stands outside the U-Bahn exit at Jungfernstieg at eleven in the morning, hands in his jacket pockets, watching pigeons peck at a dropped pretzel. Alberta arrives four minutes late, wearing a slightly too-large dark green cardigan instead of her usual lavender one, eating an apple from her tote bag as she scans the plaza for a rubbish bin.

Alberta finds a bin six metres away, deposits the core of the apple, and then comes back Sorry. Hi.
Xue Hey, don't worry about it.
Alberta stands beside Xue, looking up at the sky briefly So where are we going.
Xue We're going to the park.
Alberta Which one.
Xue The Wohlerspark[34] maybe.
Alberta That's in Altona. We're in the city centre. We could take the U-Bahn to Holstenstraße or walk through Neustadt. Takes about forty minutes on foot.
Xue Well, what do you choose?
Alberta already walking Walking.
Xue Good, let's go walking together.

Alberta walks together with Xue at a leisurely pace. She carries the tote bag on her right shoulder. They cross into Neustadt. The streets get slightly narrower, the architecture a little older, the Saturday morning foot traffic thinning out as they get further away from the city center. Then, on the side of a building at the corner of a block undergoing renovation, mounted on scaffolding high enough to be visible from three streets away, a billboard appears:

Intel Corporation · Neural Compute Architecture
Ultra-Resistant.
No Limits.
Built Different.
The processor that does not stop.
For those who push past boundaries.
Available Q3 2036
Born from the future of human potential.

The two of them stop walking at approximately the same moment.

Xue Intel...
Alberta reads it for a moment "Born from the future of human potential." quiet, without heat That's our chip.
Xue I heard that the Institute of Genetics sold their ISA to Intel so they can use for datacenters.
Alberta still looking at the billboard And they made it into... this.
Xue And look, just below where the billboard is, there is a server shop.

Directly beneath the billboard there is a narrow retail space with a hand-painted sign above the door reading SERVERHAUS HAMBURG - KOMPONENTEN & GEBRAUCHTE HARDWARE. The window is dense with products: rackmount units, cables coiled on hooks, a shelf of used SSDs in antistatic bags, a Raspberry Pi display stand. And in the front right corner of the window, propped against a used server chassis with a dent in its left panel, there is an Intel Neural Compute Architecture promotional card with the same blue as the billboard and aggressive typeface.

Alberta They're selling it right under the ad.
Xue approaches the shop and looks at the window There are actual datacenter server drawers in here. And some of them are very new, I haven't seen servers sold in a physical shop.
Alberta Is that normal? Selling servers in a regular shop?
Xue I don't know, maybe it's for the Intel promotional.

A group of three passes on the pavement behind them, two in conversation, the third glancing at the shop window and halting the group. The first two look at the window, and among them, a generated human in a yellow jacket from the group reads the Intel promotional card in the window.

The shop is closed. Saturday morning hours, a handwritten sign on the door: 11:00 - 16:00. It is 11:24. The generated human in the yellow jacket reaches the door first, tries to pull handle without really meaning to, and it opens.

Everyone looks at each other. The door is pushed open six centimetres. The smell of dust and old electronics comes out first. Then someone at the back of the group steps forward and pushes the door fully open. Glass crunches faintly under the door's arc. Then they all go in one by one.

The shop is narrow and goes further back than the window suggested. The front section is intact, but three metres in, a shelf unit on the left has partially collapsed, components scattered across the floor, bubble wrap and antistatic bags split open. A monitor on the service counter is dark but intact. The NCA units in the back sit in open shipping crates.

The generated human in the yellow jacket crouches near the collapsed shelf, looking at something on the floor without touching it.

Quiet
Generated Human
Nobody was here when this happened.
Xue I am Xue by the way.
Lena looks up, stands, brushes dust from knees, looks at Xue and then Alberta Lena. You were at the protest. I saw you with someone.
Xue Yeah, it's my friend, although I have told her to not friendzone me. She often has problems with avoidance.
Alberta examining the collapsed shelf without touching anything, she goes very still for one second, without turning around I'm right here.
Xue pulls out a server drawer slightly It's open... I know this is a standard computer, but look at the CPU, it looks like one of our former chips, or rather, your former chips, because I am not a generated human, although I am friends with one.

Lena crosses the room immediately. Two others follow. Alberta comes last, standing at the edge of the group forming around the server drawer.

The CPU module is visible through the chassis venting, a flat matte-grey package seated in a proprietary socket, considerably larger than a standard desktop processor but much smaller than a full server chip. Around its perimeter, a ring of fine-pitch connectors that do not correspond to any standard socket format. Along one edge, barely legible on the substrate in small characters: NCA / HAL-COMPATIBLE.

Lena takes out her phone and photographs it.

Thermal
Generated Human
from behind, a different voice That is not a datacenter chip. The thermal envelope[35] is wrong. Datacenter CPUs run hot, they need active cooling, you can see the heatsink specifications on the casing. This one is passively cooled. This is a low-power embedded form factor.
Xue pulls out the server some more And it's already slotted in here, and it can be removed.
Alberta leans in past Lena's shoulder It's the same extraction mechanism. Different form factor but the same release principle as the hot-swap kit the Institute shipped.
Thermal
Generated Human
crouching beside Xue It's designed to be field-replaceable. In a datacenter context you do not design for field replacement at the CPU level, you replace the whole unit. This is designed for something that gets swapped individually.
Quiet
Generated Human
reading the shipping label on the nearest open crate Consignee: Serverhaus Hamburg. Shipper: Intel Deutschland GmbH, München. pause Shipped three weeks ago. Before the public announcement.
Alberta straightens up They made it removable on purpose.
Xue clicks on the CPU tab of the server and it pops out And look at this shiny metal plate on top. It should have been dark epoxy, but it is not. And it says nothing on top.

Lena holds her phone light over it. The module sits in Xue's palm, lighter than expected. The top surface is a polished metal plate, an integrated heat spreader[36], but the alloy is wrong for a standard IHS. Too light. A slightly warm silver rather than copper-tinted. And completely blank. No Intel logo. No product marking. No serial number visible on the top face. Everyone is looking at it.

Quiet
Generated Human
very carefully and slowly Turn it over.

On the underside, the fine contact array with the pins. And along one edge, in characters small enough to require Lena's phone light to read:

NCA · HAL_ABUS READY · 65Hz · 4.42mV · CORTEX-COMPATIBLE

Alberta still looking at the markings Cortex-compatible. They printed that on the chip. pause They know the project codename.
Xue Also, there are less pins than the standard CPU.
Lena comes with her phone light, moving it slowly along each edge Four sides. Standard LGA[37] server socket has well over a thousand contacts. This has three sides with contacts. One side is blank.
Thermal
Generated Human
crouching lower The blank side is where HAL_ABUS connects. It is not a standard electrical interface, it is an analog bus. You would not put it on the same contact array as the digital signals. You would keep it physically separated.
Lena takes the module from Xue carefully, holds it up in her phone light, rotating it The blank edge has four slightly recessed pads. Very small. pause That is the analog interface. Four contacts for a differential signal pair plus ground plus carrier reference. Same as what the lab documented on the original chip.
Xue The slot itself is not standard, it could be a proprietary slot designed only by Intel.
Lena shines the phone light again into the empty socket The slot is keyed. You can see the alignment notch is asymmetric. You cannot insert a standard CPU in the wrong orientation, but you also cannot insert any standard CPU at all. This only accepts this module.
Thermal
Generated Human
Which means the servers in this shop only run NCA. You cannot retrofit them. You cannot put a standard Xeon in there. Once you buy this chassis you are on Intel's architecture permanently.
Alberta How many units are here?
Quiet
Generated Human
counts the crates Fourteen, assuming one module per chassis.
Lena looks at the promotional card in the window One partner retailer in Hamburg already has fourteen demonstration units three weeks before public announcement. pause How many partner retailers are there?

Nobody knows. Xue is still holding the module, the blank edge with its four analog pads facing upward in the phone light. The street outside passes normally. The ULTRA-RESISTANT billboard is still visible through the shop window, framed by the door left open.

Xue picks up a dusty Intel Centrino[38] from a desk in the dark and compares it with the NCA This CPU is similar in size to the Intel Centrino.
Lena The Centrino was a mobile processor with low power and small footprint, designed for laptops in the early 2000s. It was Intel's first push into efficient mobile computing. If they used the same envelope for this, they are not thinking as if it's for datacenters. Datacenters do not care about size, but throughput per watt per rack unit.
Thermal
Generated Human
A Centrino-sized chip that runs the cortical port ISA and fits in a proprietary low-power slot. pause That does not appear to be an actual datacenter chip for datacenters. That appears to be an embedded chip for datacenters.
Alberta looks at the billboard through the window Ultra-resistant. No limits. Built different. quietly They must have wrote the marketing for a datacenter product based on something else entirely.
Xue So, what the NCA really is if it's not a datacenter chip but it's used inside a datacenter server?
Lena sits down on an upturned crate A trojan horse. The server is the cover story. You sell it as datacenter infrastructure, enterprises buy racks of them, they go into server rooms, into hospitals, into universities, into government buildings. The chassis looks like a standard standard server. The procurement department sees an Intel product with an impressive spec sheet. Nobody in the purchasing chain knows what the analog interface does.
Thermal
Generated Human
standing up slowly And once it is in the building, server rooms are not monitored for analog RF emissions at 65 hertz. Nobody is looking for a 4.42 millivolt carrier signal in a rack environment. It is below the noise floor of every standard EMI compliance[39] test.
Alberta has not moved from where she is standing So, it is not a chip for datacenters. It is a chip that travels through datacenters to get somewhere else.
Lena The Institute could not implant chips in people anymore with the court order. pause So Intel built them an indirect one.
Xue Can we take pictures and send them to the reverse-engineering community?
Lena already photographing Already started. without looking up from her phone But we should be systematic. Every surface of the module, the socket, the chassis spec plate, the shipping label, the promotional material, the blank edge contacts. Everything.

The group reorganizes itself. The quiet person takes the shipping crates. The thermal person photographs the chassis spec plates one by one. Two other two document the socket from every angle, using each other's phone lights. Alberta takes the NCA module from Xue carefully and holds it steady while Lena photographs the underside contact array in sections, overlapping frames.

Alberta rotating the module slightly for a better angle on the blank edge, quietly, then to Xue We came here for a walk.
Xue Yeah, but now that we stumbled upon new technology...
Alberta the smallest smile, still holding the chip steady for Lena's camera The park can wait.
Xue We could take a walk together, all of us, if we want, maybe.

Lena lowers her phone and looks at the group. A few nods, a shrug from the thermal person, the quiet one already uploading photos.

Lena I know that park. puts her phone away Give me two minutes to finish the upload.

The group waits for the upload to finish. Someone finds a relatively clean spot on the counter to lean against. The thermal person reads the chassis spec plate one more time, quietly, to themselves. Alberta carefully reinserts the NCA module into its socket with a soft click, pushes the server drawer back in and then looks again at Xue.

Alberta If we have been here, maybe we should tell the lab after all.
Xue We already started doing that, you know...
Alberta pauses I meant Felix and the others specifically. Not just the forum.

Lena's upload completes. She pockets her phone and then they all exit the shop and make sure the door is closed.

IX · II
Wohlerspark

The group walks from Neustadt to Altona. Jonas has already pulled up the Cortex Project forum on his phone and is reading the first replies to the upload.

Alberta is beside Xue and she has moved the tote bag to her left shoulder. The street opens as they cross into Altona-Altstadt, the architecture becoming older and lower.

Alberta without preamble You told a stranger I friendzone you.
Xue No, I told that I told you to not friendzone me. I haven't thought much about that.
Alberta a pause There is a difference.
Xue What difference?
Alberta looks at the pavement briefly, then back forward One means you told her what I do. The other means you told her what you want.
Xue Let's just get over my anxieties and my love for you.

Alberta does not answer immediately. They walk for half a block.

Alberta quietly Okay.

Xue to Maya So, what do you usually like to do?
Maya looks up from her phone, slightly surprised, puts it away I read a lot. Mostly history. The kind that gets written over.
Xue And I also read history, but not much, and largely contemporary history.
Maya Contemporary is harder. The sources are alive. They argue back.
Xue Actually, older history is harder because of scarcity and partial irrelevance.
Maya considers for a moment Fair. Though with older history at least everyone who was wrong about it is dead.
Jonas looks up from his phone Twelve replies on the forum already. Someone in Dortmund is asking if we have the chassis serial number.
Xue No, we don't, we looked at the chassis like grave robbers.
Lena a short genuine laugh We were grave robbers. Very careful ones who put everything back.
Jonas typing the reply I'm telling them we have photographs of the spec plate. That should have it.
Alberta quietly, to Xue Grave robbers who then went to a park.
Xue It's going to be a disaster for Intel's PR.
Maya half to herself It already is. Someone posted the photos to three other forums while we were still in the shop.
Jonas still reading There is a thread on Hacker News[40]. Forty-seven comments. The top one says this cannot be real and the second one says it is real, here is the HAL_ABUS spec from the Cortex Project paper.
Lena looks at the sky Intel announced a datacenter chip and within four hours the internet established it is a neural interface chip in a rack unit. Their communications team is going to have a very bad Monday.
Xue Sure, and the open-source community is going to have a very good day. Reverse-engineers are one of the smartest people out there, or so I think.
Maya Or the most stubborn. Sometimes it is the same thing.
Alberta to Xue, quietly You think that about the OpenCortex people too?
Xue Yeah. And actually, it's OpenCortex now, not the Cortex Project.
Alberta not quite a smile OpenCortex. You've been following it closely.
Xue The news are all over the place.
Alberta quietly I know. I just didn't know you were following it for the same reasons I am.
Xue Information Technology seems to be a common passion these days among generated humans.
Alberta It's not really a passion when it's also your situation.
Maya from slightly ahead, having heard Some of us came to it the way you come to anything that was used against you. You learn it because you have to, and then you find you are good at it, and then it is not just necessity anymore.
Jonas without looking up I started because I wanted to understand the paper. I am a history student. I understood maybe a third of it. It was enough.
Xue I had a passion for IT since I was 12, a long time ago, and I don't think myself as a good programmer, although I have made complex local web programs with LLMs.
Alberta 12 is a long time to spend on something you don't think you're good at.
Xue Yeah, but at the same time I think I am good at understanding programs and I recently started studying x86 assembly, although that's a mess.
Lena over her shoulder x86 assembly is a mess because it is thirty years of backward compatibility stacked on top of itself. It was a mess in 1995. It is a more organised mess now.

They turn a corner and the street opens into a wider residential stretch, trees lining the pavement, the traffic quieter. Wohlerspark is a few minutes ahead, visible as a gap in the buildings where the green starts.

Jonas still on his phone Someone from the OpenCortex repository just commented on the Hacker News thread. They confirmed the CORTEX-COMPATIBLE marking is consistent with the HAL_ABUS four-contact spec they published. They are asking if anyone has tested whether the NCA responds to a 65 hertz signal.
Lena looking at the park entrance ahead Nobody has a DAC on them.
Jonas I have a function generator app on my phone. It was for a music project. I never finished the music project.
Xue Let's use the app.
Lena already stopped walking We don't have the chip anymore. We put it back in the chassis.
Jonas The chassis is in a locked shop.
Maya That we left unlocked.

Everyone looks back the way they came.

Alberta to Xue, quietly We are not going back.
Xue I know, but if we can generate signals according to the documentation...
Alberta considers A phone speaker in the open air is probably not going to produce 4.42 millivolts on a HAL_ABUS analog bus.
Xue Oh... I forgot...
Lena not unkindly The app would need to drive a DAC. The DAC needs to be physically connected to the chip's analog interface. The phone speaker produces sound pressure, not electrical potential. It is a good instinct though.
Jonas puts his phone away, looks at the park entrance We document what we have. Someone with the right equipment will follow up. That is how this works.
Maya already walking again toward the entrance The park is still there.

She goes through the gate. The others follow one by one.


Wohlerspark used to be a cemetery, its last burial in 1945, converted to public green space in 1979. The linden alleys are old and high. The weathered gravestones remain along the edges, pale and slightly tilted.

Jonas reads a gravestone as he passes it 1847. Someone was here a long time before any of this was a problem.
Xue Computers are a modern invention, although I had a dream where people in the late 19th century were grappling with the limits of 8-bit computing and created 32-bit computers.
Jonas Computers are a modern invention. The dream is wrong on the timeline but not on the pattern. Every generation hits the limits of what they have and builds the next thing out of frustration.
Xue Also, who uses X11[41] and Wayland[42]?

Everyone raises their hand. Including Xue. Including Alberta, after a brief pause.

Lena looks at Alberta's raised hand You use Linux.
Maya hand still up X11. I know Wayland is the future. I am not ready.
Jonas Wayland. Two years ago I finally made the switch and I spent a week fixing screen sharing.
Lena Wayland. It was painful and I would do it again.
Alberta to Xue, quietly, on the path between the gravestones and the linden trees You didn't hesitate.
Xue And what distributions do you use? I use Debian.
Alberta Trisquel[43]. It came preinstalled on my laptop for some reason. I have never investigated why.
Jonas genuinely delighted The FSF would be very happy. Fully free software, no proprietary blobs. Your laptop manufacturer made a very unusual decision.
Lena Fedora. I switch every few years out of stubbornness.
Maya to Xue Debian also. Stable or testing?
Xue Stable.
Jonas Ubuntu. But I disable all the Canonical telemetry and the Snap store integration immediately after installation. So essentially Debian with extra steps.
Lena walking ahead between the gravestones That is not essentially Debian with extra steps. That is Ubuntu with self-inflicted complications.

They reach the central clearing. The linden trees close overhead.

Alberta stops in the middle of the path, looks up at the trees It was a cemetery.
Xue Yeah, and Intel Cortex's will become a graveyard, or so I think if it's that similar to Itanium in presentation.
Lena stops beside Alberta, also looking up Itanium was technically superior to x86 in almost every measurable way. Intel spent fifteen years and billions of dollars on it. It failed because the ecosystem did not follow. Developers did not rewrite their software. The compilers were never quite right. The performance never materialised in practice the way it did in benchmarks.
Maya sits down on a bench at the edge of the clearing The NCA has the opposite problem. Itanium failed because nobody wanted it. The NCA is something nobody was supposed to want and people are already very interested in it for reasons Intel did not intend.
Jonas The Cortex Project already published a partial spec. OpenCortex already has a coreboot payload. The ecosystem is forming before Intel's official launch. They may have accidentally created the conditions for their own open alternative by acquiring something the community was already working on.
Alberta looks at the gravestones around the clearing Itanium is buried somewhere. Maybe here.
Xue Not here, but could be. And also, Intel actually purchased the architecture from the Institute of Genetics.
Jonas Which makes it worse for them legally. They bought an architecture already subject to a court disclosure order, already partially documented in a peer-reviewed paper, and already reimplemented in an open-source project. They spent 340 million euros to acquire something the community was in the process of liberating anyway.
Maya from the bench The court order follows the ISA to whoever holds it. Judge Vasilescu was very clear about that.
Lena sits down on the bench opposite Maya So Intel bought a liability with a processor attached.
Alberta quietly, not to the group Do you think they knew what they were buying.
Xue Intel follows whatever is most profitable, and supports the Trump administration like every other tech company because it is advantageous to them.
Jonas The US government bought a nine billion euro stake in Intel, ten percent of the company. So when you say Intel supports the Trump administration, the more accurate statement is that the Trump administration is part-owner of Intel.
Maya Which means the NCA is a chip developed from an architecture acquired from a European public institution, manufactured by a company ten percent owned by the United States federal government, being sold to European hospitals and universities.
Lena very flat And marketed as ultra-resistant.
Jonas The court order still applies, and the case of a German administrative court versus a company partially owned by the US government is going to be interesting.
Maya The FSF campaign is European, the lawsuit is European, the Cortex Project is European and the chip with the original ISA was European. Intel bought it and made it American. looks at the gravestones And now it is in European server rooms.
Alberta to Xue, quietly Still think it will be a disaster for their PR?
Xue Yeah, still think it will be a disaster, and the chip is not yet in server rooms, only those datacenter prototypes like the ones we found at the store.
Alberta Fourteen units in one shop in Hamburg. We don't know how many shops.
Xue I agree, there could be even more units.
Jonas sits down on the grass, phone in hand Someone just replied on the forum. They found the Intel partner retailer page. There are thirty-seven registered NCA partner retailers in Germany. Eleven in France. Eight in the Netherlands. Six in Poland.
Maya Demonstration units only. That is what the sign in the shop said. Fourteen per retailer if our shop is representative. Thirty-seven retailers in Germany alone.
Lena the arithmetic is not complicated That is a lot of demonstration units for something not yet publicly announced.
Alberta quietly, to Xue We came here for a walk and now there are five hundred chips in German server shops.
Xue We came here for a walk to hang out, not necessarily to investigate those units.
Alberta looks at Xue I know. We can still just be here.

She sits down on the grass beside where Jonas is sitting. Lena leans back on the bench. Maya has her eyes closed, face tilted toward the sky through the linden trees. The forum replies keep coming. Jonas turns his phone face down on the grass in the afternoon.

Itanium II

Intel Deutschland GmbH, Munich. Monday, 07:43. The third-floor Schwabing office was designed to feel open and collaborative but currently feels like a pressure vessel, its floor-to-ceiling windows catching the morning light at the wrong angle for everyone sitting at screens. Nine people are in the room, four called in before six, gathered around a central table covered in printouts of a Hacker News thread with four thousand comments and growing, which has sat on the front page for thirty-one hours: "INTEL NCA IS A NEURAL INTERFACE CHIP BUILT ON A PROPRIETARY BRAIN ISA CURRENTLY SUBJECT TO A GERMAN COURT DISCLOSURE ORDER."

The head of European communications, Petra Haugen, stands at the window with her phone, having been on calls since five forty-five. She ends the current one and turns to the room.

Haugen Santa Clara wants a statement by nine. European press wants a statement by eight. looks at the Hacker News printout Der Spiegel, FAZ, Le Monde, the Guardian, and Politico Europe all have the chip photos.

A short pause. Someone at the back of the room makes a sound.

Haugen We also have a problem that is specifically European and that Santa Clara does not fully understand yet. sets her phone down Someone walk me through it.

A man in a grey pullover, Stefan Brandt, senior regulatory affairs, stands up without being asked.

Brandt The court order. VG Hamburg 7 K 2891/26. Judge Vasilescu ruled that the ISA disclosure obligation follows the asset to whoever holds it. We knew this when we completed the acquisition. Legal said we had twelve to eighteen months to challenge it before it became actionable. pause That was before someone photographed fourteen NCA units in a Hamburg server shop three weeks before our public announcement and posted it to the Cortex Project forum at 11:47 on a Saturday morning.
Haugen Which means.
Brandt Which means the court now has evidence that we are actively deploying hardware based on the disputed ISA into the European market before complying with the disclosure order. We are not in a challenge period anymore. We are in contempt territory.

A younger woman near the door, Karen Fischer, communications, looks up from her laptop.

Fischer There is also the GDPR angle. The chip's HAL_ABUS interface processes neurological data. Several MEPs have already sent letters to the European Data Protection Board asking whether the NCA requires a Data Protection Impact Assessment before commercial deployment. That question did not exist on Friday.

Haugen picks up her phone and then then puts it down.

Haugen What is the Cortex Project forum saying right now?
Fischer reads from her screen The top-pinned post reads: "Intel deployed CORTEX-COMPATIBLE hardware into thirty-seven German retailers before complying with a court order requiring ISA disclosure. The OpenCortex clean-room reimplementation predates the deployment. We have part of the spec, the hardware photos, the court documents and they have a billboard." pause It has fourteen thousand upvotes.
Haugen Get me the legal team, the regulatory team, and someone who actually understands what HAL_ABUS does. Not the marketing brief. Someone who has read the paper. picks up her phone And get me Santa Clara. Because I need to explain to them what a Verwaltungsgericht is before nine o'clock.

The news read in the room:

Spiegel Online - Technologie
Intel-Chip entpuppt sich als Gehirn-Interface: Gericht fordert Offenlegung
Interne Dokumente und Fotos aus einem Hamburger Serverhandel zeigen, dass Intels neuer NCA-Prozessor auf einer proprietären Schnittstelle basiert, die ursprünglich für neuronale Implantate bei gedruckten generierten Menschen entwickelt wurde. Das Verwaltungsgericht Hamburg hatte bereits im vergangenen Jahr angeordnet, dass die vollständige Befehlssatzarchitektur offengelegt werden muss, eine Verpflichtung, die nun auch für Intel als neuen Eigentümer gilt.
(Intel's new chip turns out to be a brain interface: court demands disclosure. Internal documents and photographs from a Hamburg server retailer show that Intel's new NCA processor is based on a proprietary interface originally developed for neural implants in printed generated humans. The Hamburg Administrative Court had already ordered full disclosure of the instruction set architecture last year, an obligation that now applies to Intel as the new owner.)
The Verge
Intel's "Neural Compute Architecture" chip has CORTEX-COMPATIBLE printed on it and is subject to an active German court order
The NCA, Intel's quietly announced datacenter accelerator, carries a substrate marking reading "NCA · HAL_ABUS READY · 65Hz · 4.42mV · CORTEX-COMPATIBLE", a direct reference to the Cortex Project, the volunteer reverse-engineering effort that spent months characterizing the same chip architecture now being sold as an AI accelerator. The chip was photographed in a Hamburg Serverhaus three weeks before Intel's public announcement. The shop had fourteen units. There are thirty-seven Intel NCA partner retailers in Germany alone.
The HAL_ABUS specification referenced on the chip's substrate was published by the Cortex Project in a peer-reviewed paper that Intel almost certainly read before closing its €340 million acquisition of the Institute of Genetics ISA portfolio.
It gets worse. The ISA is currently subject to a disclosure order from the Verwaltungsgericht Hamburg. Legal experts contacted by The Verge say the order almost certainly applies to Intel as the current holder. "They bought a court order along with the chip", said one IP attorney familiar with the case, who asked not to be named. "That is not a position you want to be in three weeks before your product launch."
Politico Europe - Tech & AI Policy
MEPs demand GDPR review of Intel's neurological data chip before European rollout
A cross-party group of twelve Members of the European Parliament has written to the European Data Protection Board requesting an urgent ruling on whether Intel's NCA processor requires a mandatory Data Protection Impact Assessment before commercial deployment in EU member states. The chip's HAL_ABUS interface, documented in a peer-reviewed paper by the University of Siedlischte's Cortex Project, is designed to process analog neurological signals at 65 hertz, the frequency associated with conscious attention in biological neural tissue.
"This is not a datacenter chip. This is a chip that was surgically removed from the brains of generated humans by court order, rebranded, and sold to European hospitals and universities as infrastructure. The GDPR implications are not theoretical", said MEP Friederike Albrecht (Greens/EFA, Germany)
Intel has not responded to requests for comment.
Frankfurter Allgemeine Zeitung
Datenschützer prüfen Intel-Chip nach Cortex-Enthüllung
Nach der Veröffentlichung von Fotos aus einem Hamburger Fachhandel, die Intels neuen NCA-Prozessor mit dem Aufdruck "CORTEX-COMPATIBLE" zeigen, haben mehrere europäische Datenschutzbehörden angekündigt, die Rechtmäßigkeit der geplanten Markteinführung zu prüfen. Der Chip basiert laut Gerichtsdokumenten auf derselben Befehlssatzarchitektur, deren Offenlegung das Verwaltungsgericht Hamburg im vergangenen Jahr angeordnet hatte.
(Data protection authorities examine Intel chip after Cortex disclosure. Following the publication of photographs from a Hamburg specialist retailer showing Intel's new NCA processor marked "CORTEX-COMPATIBLE", several European data protection authorities have announced they will examine the legality of the planned market launch.)
Hacker News - Top Comment · 41,203 points
throwaway_cortex_dev: I want to be very clear about the timeline here. The Cortex Project published HAL_ABUS electrical specs in a peer-reviewed paper. Intel read that paper, acquired the ISA, printed CORTEX-COMPATIBLE on the chip substrate, shipped demo units to 37 German retailers and did not comply with the court disclosure order. The community published a clean-room reimplementation before Intel's product launch. Intel's PR team is now explaining to their Munich office what a Verwaltungsgericht is.
↩  You skipped IX · III: Itanium II

Intel's European communications office assembles on a Monday morning to manage the fallout. Photographs of NCA chips in a Hamburg server shop, posted to the Cortex Project forum and amplified on Hacker News, predate Intel's public announcement. Legal concludes this places Intel in contempt of the VG Hamburg disclosure order rather than within the expected challenge window. Parallel GDPR questions about the HAL_ABUS interface surface from MEPs to the European Data Protection Board.

Stronk eG

The consortium announcement comes on a Thursday, seventeen days after the emergency injunction halted NCA deployment across the EU. It arrives as a joint press release, six corporate logos (Intel, Microsoft, Google DeepMind, IBM Research, SAP, Qualcomm) arranged in a row above the headline.

Joint Press Release
Leading Technology Companies Announce Open Innovation Consortium for Neural Compute Architecture
Overview
Intel Corporation, Microsoft Corporation, Google DeepMind, IBM Research, SAP SE, and Qualcomm Incorporated today announced the formation of the Neural Compute Architecture Consortium (NCAC)[44], a multi-stakeholder licensing body that will govern access to the Neural Compute Architecture instruction set portfolio under a shared proprietary framework. Consortium members will gain full access to the ISA documentation, including the previously undisclosed HAL_ABUS specification, under terms to be negotiated with the relevant regulatory and judicial bodies.
On Open Source
The consortium does not contemplate open-source licensing of the ISA at this time. Members believe that the sensitivity of neural interface technology requires controlled access under a managed licensing framework. The consortium welcomes dialogue with the open-source community and will establish an advisory panel.
On the Court Proceedings
The consortium is in active dialogue with the Verwaltungsgericht Hamburg and has requested a stay of proceedings pending the consortium's formal establishment. Members believe the consortium structure satisfies the spirit of the court's disclosure order by making the ISA accessible to a broad group of qualified technical organisations.
The Neural Compute Architecture Consortium will be formally incorporated within sixty days.
"They made a propietary club of six companies with an advisory panel for open source which I cannot understand." · Cortex Project forum
"The consortium satisfies the SPIRIT of the disclosure order. But only the spirit, not the order." · Cortex Project forum

The consortium announcement lands on a Thursday. Stronk is incorporated on Friday. The founding document, filed with the Hamburg commercial register at 16:47, lists the entity type as eingetragene Genossenschaft[45] (a registered cooperative) and gives the registered name as STRONK eG. The articles of association, posted publicly to a GitLab repository at 16:48, one minute after filing, begin with the following preamble:

The membership fee of one euro is paid, in the first twenty-four hours, by forty-one thousand, two hundred and fourteen people. By the end of the first week, two hundred and nineteen thousand members joined in the cooperative and two hundred and nineteen thousand euros have been paid. The GitLab repository for the articles of association has been forked six hundred times. Someone has added a CONTRIBUTING.md. Someone else has added a CODE_OF_CONDUCT.md. A third person has added an issue titled "should we have a logo" which has forty-seven comments.

The logo question is resolved on day four when a generated human graphic designer from Brno submits a pull request containing a simple geometric mark: a raised fist, but the fist is made of circuit traces. The PR description reads: "it is extremely on the nose. that is the point." It is merged within an hour.


In the IT lab at the University of Siedlischte, Koko is reading the Stronk articles of association on screen. The wall sheet behind them reads 65Hz - FULL_EXEC and 106μs - SPARC WINDOW = LFP RESPONSE and WHOEVER BUYS IT STILL HAS TO ANSWER TO THE COURT.

Felix reads over Koko's shoulder.

Felix They named it Stronk.
Mira reading the preamble on her own screen "Consortiuming" is not a word.
Ryo It is now. It is in a legal document filed with the Hamburg commercial register.
Dani looking at the membership counter They have collected more money in forty-eight hours than we collected in eighteen months.
Priya We seeded this. Our paper, our spec, our forum, our repository. pause They are buying the ISA with the community we built.

A pause in the lab.

Felix Is that a problem?
Priya considers for a moment No. pause I just want to note it.
Koko The membership fee is one euro.
Ryo already on the membership page Paid.

One by one, everyone in the lab pays one euro. The counter moves seven times.


The legal question is real and nobody is pretending otherwise. Stronk has money but it does not yet have a mechanism to acquire the ISA as Intel has not offered to sell, the consortium is not yet incorporated and the court proceedings are ongoing. The CJEU[47] referral has been accepted and will take between eighteen months and three years to resolve.

What Stronk has, besides money and a logo and a legally filed preamble that uses the word "consortiuming", is a lawyer. Her name is Dr. Amara Diallo, Brussels-based, specialising in EU competition law and intellectual property. She joined Stronk as a member on day one for one euro and posted a thread to the forum on day three.

"Path B is the most chaotic good legal strategy I have ever read and I am a lawyer. I joined Stronk immediately after reading the full strategy." · @IP_atty_brussels
↩  You skipped IX · IV: Stronk eG

Six major technology companies announce the Neural Compute Architecture Consortium, a proprietary licensing body they argue satisfies the spirit of the disclosure order without open-sourcing the ISA. The next day, Stronk eG incorporates in Hamburg as a registered cooperative with a one-euro membership fee, articles of association ending in "Ciao stronzi," and a logo of a fist made of circuit traces. Within a week, two hundred and nineteen thousand members have joined. The cooperative's lawyer Dr. Amara Diallo publishes a four-path legal strategy: make a good-faith offer Intel will refuse, buy into the consortium and breach its license by publishing under GPL v3, file an Article 101 TFEU competition complaint, and stand ready if the courts compel disclosure first.

Path B

Xue's room, eight months after Stronk's incorporation

Eight months after Stronk's incorporation, the Neural Compute Architecture Consortium formally grants membership to Stronk eG. The decision takes four board votes, two legal opinions, one emergency meeting called by Microsoft's representative, and a letter from the European Commission's Directorate-General for Competition noting that the consortium's membership criteria were under review as part of an ongoing Article 101 TFEU examination.


It's evening in Xue's room. The Microsoft BUILD[50] 2036 keynote stream is open in one tab. It began forty minutes ago. The arena in Redmond is full. Brad Mercer, Microsoft's CEO since 2031, is walking across a stage the size of a tennis court, microphone in one hand, the other jabbing the air, jacket off, sleeves rolled up, the collar of his shirt visibly darker than it was at the start.

Mercer to the arena Windows 12 is the future. pause for applause And I don't care what anybody on Hacker News says. I don't care what some cooperative with a funny name... stops himself, recalibrates I don't care what the open-source community thinks about the future of computing. You know what the open-source community has? A forum. You know what Microsoft has? spreads arms wide Four hundred million enterprise users. FOUR HUNDRED MILLION.
Mercer Linux is great. said in a tone that communicates the opposite Linux is wonderful. I use it myself sometimes. On a server. In a data center. Where it belongs. But when my mom wants to open her email, when YOUR mom wants to open her email, she is not going to configure a display manager. She is not going to choose between seventeen desktop environments. She is going to click the Windows button and it is going to work. Because that is what we do.
Mercer Now. I want to address something directly. Because I am not going to pretend it isn't happening. Some of you have read about the Neural Compute Architecture situation. Some of you have read about a company called very deliberate pause Stronk.

A ripple with few laughs and uncertain looks occurs through the audience.

Mercer I want to be clear. Microsoft joined the Neural Compute Architecture Consortium because we believe in responsible governance of transformative technology. We believe neural interface architecture should be in the hands of people who understand enterprise security. People who understand compliance. People who understand what it means to deploy technology at scale responsibly. voice rising Not, and I want to be very precise here, not a cooperative funded by internet donations that named itself after an Italian insult and whose legal strategy is, and I am quoting their own published document, "Path B: we violate the license and accept the legal consequences".
Mercer That is not a technology strategy. louder, starting to pace You know what Stronk's plan is? Get in the room, break the rules, and hope the lawyers take longer than the mirrors. That is not how enterprise technology works. That is not how you protect users. That is not how you build trust. And trust... turns to the big screen showing the slide TRUST IS THE PRODUCT ...is the product.
Mercer walks to the edge of the stage, sweating Windows 12 is shipping to enterprise customers in Q1. The neural compute integration layer for enterprise, built on responsibly licensed, properly governed NCA architecture, will be available to certified hardware partners in Q2. This is the future. This is what responsible innovation looks like. And nobody, pointing at the camera literally nobody is going to GPL-license their way into our ecosystem.

The arena applauds. Xue's cursor hovers over the comment section.

@EnterpriseITPro
11 minutes ago
Mercer is right that Linux isn't ready for consumers. I've been saying this for years.
👍 412 · Reply ▸ 3.1K replies
@generated_22
10 minutes ago
"responsible governance of transformative technology" is what they called the chip implantation program too. just so everyone remembers.
👍 102.4K · Reply ▸ 9.8K replies
@NCA_Actually
9 minutes ago
The NCA architecture is currently subject to TWO active court proceedings and a CJEU referral. "Responsibly licensed" is doing a lot of work once again.
👍 54.7K · Reply ▸ 4.2K replies
@IP_atty_brussels
7 minutes ago
As the lawyer who called Path B "the most chaotic good legal strategy I have ever read", I want to clarify that "accept the legal consequences" is itself a legal strategy. We have prepared for this and we are ready.
👍 71.3K · Reply ▸ 5.9K replies
@LinuxOnDesktop
6 minutes ago
Linux market share on consumer desktops is 23% this quarter. "Where it belongs" is apparently everywhere now.
👍 38.9K · Reply ▸ 2.7K replies
@stronk_member_41207
5 minutes ago
he said our name on stage. maybe we have already won something
👍 93.1K · Reply ▸ 8.1K replies
@TrustIsTheProduct
4 minutes ago
they put TRUST IS THE PRODUCT on a slide at a conference about neural interface technology that is subject to a GDPR investigation. I am going to lie down.
👍 147.6K · Reply ▸ 12.3K replies
@quietvoice_gen
2 minutes ago
i am one of the four hundred million. i would like to not have neural interface architecture in my operating system without knowing what it does. just so that's on the record.
👍 188.4K · Reply ▸ 14.7K replies

Xue opens four more tabs. The other consortium CEOs have all made statements in the last ninety minutes, timed to the BUILD keynote.

Google DeepMind - Company Blog · 14:00
Wei Sheng, CEO
Google DeepMind joined the Neural Compute Architecture Consortium because we believe the future of AI inference requires novel analog compute substrates, and the NCA portfolio represents a meaningful step toward that future. We are committed to working constructively with regulators and the court process to ensure that deployment of NCA-based technology meets the highest standards of transparency and data governance. We note that the CJEU referral process is ongoing and we respect its outcome.
Qualcomm - LinkedIn · 14:07
Amir Farhoudi, CEO
Qualcomm's participation in NCAC reflects our commitment to the next generation of edge computing architectures. NCA's low-power embedded profile is precisely what the mobile and IoT ecosystem needs. We are confident that the consortium governance framework provides the technical rigour and IP protection required for responsible commercialisation. On the Stronk situation: we do not comment on ongoing litigation.
IBM Research - Press Release · 14:15
Elena Novak, CEO
IBM Research has studied the NCA architecture's register file design with considerable interest. The IBM Z coprocessor conventions embedded in the ISA's r-type namespace reflect decades of our own architectural research. We joined NCAC to ensure that this heritage is built upon responsibly and with appropriate governance. IBM supports the principle of broad ISA access within a structured framework. We also support the right of courts to adjudicate IP questions through their proper processes.
SAP SE - Statement to German Press · 14:22
Friedrich Stein, CEO
As a German company operating under German law, SAP takes its obligations regarding the Verwaltungsgericht Hamburg proceedings with the utmost seriousness. We joined the Neural Compute Architecture Consortium in good faith as a means of broadening ISA access beyond a single corporate actor. We note that Stronk eG is also a German-registered entity and we respect its legal standing. SAP has no comment on Stronk's consortium membership application.

Xue opens the chat.

Xue
sends the BUILD keynote link, the four CEO statements, and the comment thread with the TrustIsTheProduct screencap in quick succession
20:14
Alberta
"trust is the product"
20:19
Xue
Of course it is. And I really love Microsoft. Of course I am joking. Do you remember Ballmer?
20:20
Alberta
I know who Ballmer is. Mercer has better hair.
20:21
Xue
Yeah, that's the only difference.
20:21
Alberta
And Ballmer never tried to put a brain chip in the Windows kernel.
20:22
Xue
Of course, that's impossible. And remember the Microsoft store discourse in the little Symposium?
20:23
Alberta
The Institute is the Microsoft store. The consortium is also the Microsoft store now. It's Microsoft stores all the way down.
20:24
Xue
At Microsoft, you...
20:25
Alberta
...you cannot disable the telemetry, cannot use a local account, cannot open OneDrive without it moving your files to the cloud, cannot update without it installing things you didn't ask for, cannot screenshot something without the AI saving it in plaintext next to your passwords, and now apparently cannot have a brain without it being CORTEX-COMPATIBLE. The Institute really did copy them.
20:27
Xue
And Microsoft appears so many times in the Symposiums... they have really fell in love with them.
20:28
Alberta
The Institute presented themselves as not-Microsoft and then sold the chip to Microsoft's friends who are also trying to be Microsoft.
20:29
Xue
And then related to love, for some reason I have been trying to avoid saying something about you...
20:31
Alberta
Say it.
20:34
Xue
And that is that I love you, but fine...
20:36
Alberta
I know.
20:41
I love you too. I'm just slow at it.
20:41
Xue
I wish I had a really long hug with you and just escape from those confrontations.
20:43
Alberta
Come over then.
20:44
Xue
But how, we're in messages.
20:45
Alberta
I meant in general. Not right now.
20:46
But soon.
20:46
Referenced episode
▶
Friendzoned - Episode 7 · "When The Girl Who Friendzoned You, Finally Becomes YOUR GIRLFRIEND"
Manual transcript for reference
Claire Oh my god, it's really easy. You're just going to go up there and be like: Emily, you are boring, I don't love you, I wanna be with Claire because she's hotter and way cooler than you and I love her.
Mikey Yeah, yeah, yeah, okay, no, I'm not going to say any of that.
Claire I just- Okay, let's roleplay...
- silence and tensioned atmosphere -
Claire Wait, what just happened?
Mikey Claire, I don't think pretending you're a hot teacher is going to help right now.
Claire What?
Mikey But I'm down for roleplay if you want to, I... I can be the hot teacher if that's-
Claire That's what I am not talking about. Pretend I'm Emily and then practice breaking up with me.
Mikey Oh...
Claire Yeah...
Mikey For the breakup...
Claire For the breakup.
Mikey For the breakup. Okay.
Claire Okay, go.
Mikey Um, Emily, I need to talk to you.
Claire Oh no, wow, that sounds so serious.
Mikey I think we need to break up.
Claire Oh wow, that sucks, I'm a little sad but you're way smarter than me and I'm just a stupid girl so I guess you have a good point, we should probably break up, thanks for telling me, you're a really nice guy...
It's going to be so easy.
Mikey Okay, but what if she doesn't say that and instead she gets really sad and I feel really horrible about myself cuz I'm leaving a girl I've been with a year for a girl who like has broken my heart a million times, what about that situation?
Claire Mikey, you are driving me crazy.
Mikey Sorry...
Claire You have to go for what you want, okay? So, take what you want. What do you want?
chat continues
Xue
And have you watched the Friendzoned series all this time?
20:48
Alberta
Yes. I watched episode 7 again actually.
20:50
The one where Claire makes Mikey practice breaking up with Emily.
20:50
Xue
And how that was?
20:51
Alberta
Deeply uncomfortable. Claire tells him to just say Emily is boring and he doesn't love her and he wants to be with Claire because she's hotter and way cooler. And Mikey just says he's not going to say any of that.
20:53
And then Claire says let's roleplay and there's this silence and then everything goes bad immediately.
20:53
Xue
What would you do if for example you love me but also someone else?
20:55
Alberta
I don't.
20:58
But if I did I would tell you instead of making you practice a breakup with me while pretending I'm someone else.
20:58
Xue
Why does Claire want Mikey to practice breaking up with Emily besides making Mikey love her, when Mikey of course is going to be with other girls in the series?
21:00
Alberta
Because she wants him to choose actively. Not drift toward her because Emily is gone but actually say out loud that he wants Claire specifically. The breakup practice is just an excuse to hear him say it.
21:03
Which is why it goes so bad. He almost does.
21:03
Xue
And Claire also has a mock attitude, so...
21:04
Alberta
So she'd rather make it a scene than admit she wants to hear it straight.
21:05
I recognise that.
21:05
Xue
She tells Mikey multiple times that she loves him, and also says she can tolerate another ten years of friendship, but that's not what she wants.
21:07
Alberta
I've been doing a version of that.
21:12
Minus the ten years.
21:12
Xue
How?
21:13
Alberta
Making it a scene instead of just saying it.
21:15
I said it eventually though.
21:15
Xue
You were running away from me all the time, that's what the scenes were.
21:16
Alberta
I know.
21:19
I'm not going to do that again. I mean it this time.
21:19
You've been patient enough.
21:20
Xue
I've been more desperate for you than patient.
21:21
Alberta
That's more romantic than patient.
21:22
Come over soon.
21:22
Xue
Again you say that, fine, I will, but then don't make those figures from the game Emily is Away where Emily wants to get closer, the user accepts to invite her, and then Emily says the users hooked up with her and didn't want to. Or inverse, the user tells her to arrive as just a friend, and then Emily says she wished for some more.
21:24
Alberta
a moment later, after looking it up Emily is Away is a 2015 chat simulation.
21:27
Emily keeps reframing what she wants depending on what you say, so whatever you choose feels wrong. That's horrible.
21:28
I'm not going to be that Emily. I know what I want. I just took too long to say it out loud.
21:29
Xue
Good, and again, I know what I want, I just want even more time spent with you only.
21:30
Alberta
Stop being non-committal about it. If you want more time with me, say you want more time with me. Not "I want more time spent with you only" like you're reading from a legal document.
21:31
Xue
Okay, I want to go, be really close to, a cuddle, a hug, something, just so I can say anything to you.
21:33
Alberta
Then come over tomorrow. I'll be home.
21:34
Xue
I expected more like be in the park, but fine...
21:35
Alberta
The park is also fine. Wohlerspark again if you want, there's more gravestones to compare to Itanium.
21:36
Xue
Not Itanium, let Stronk do their work.
21:37
Alberta
Fair. We can just sit there then.
21:37
Xue
It was way cooler if you were going to be like Claire.
21:39
Alberta
Okay listen.
21:41
You want more time with me. I want more time with you. We both know this. So stop treating it like a weather forecast. You're going to show up and I'm going to be there and we're going to sit on a bench that is definitely not a gravestone and you're going to say whatever it is you've been trying to say and I'm going to say some things back.
21:42
What do you want?
21:42
Xue
I want to squeeze you all the time.
21:44
Alberta
That's specific.
21:45
Also, bring a jacket, it's going to be cold.
21:45
Xue
But wait, the tension resolved suddenly, it's hard to make a romcom.
21:46
Alberta
I'm not Claire. I don't actually know how to do the thing where the tension stays and also moves forward at the same time. She's very good at that. I just get to a point and then I say the thing.
21:48
Xue
And I'm sure you're not that unstable...
21:49
Alberta
Claire keeps Mikey at exactly the distance where he can't leave but also can't arrive. The whole arc is engineered so he can never actually relax.
21:51
I don't want to do that to you. I've already done enough of the pulling away version.
21:51
Xue
And Mikey also keeps her at a distance, so we have similar segments. At season 3, episode 4, Claire kisses Mikey, representing a temporary change in the arc that has otherwise been the same. And the entire arc centers around the girl who initially friendzoned Mikey but then fell in love with Mikey and tries to make Mikey fall in love to her by force.
21:53
Alberta
The difference is you haven't moved on. Mikey has Emily. You just kept showing up.
21:56
And I tried to friendzone you and then realized I didn't actually want to. Nobody had to kiss anybody to make that happen.
21:56
Also I was not trying to make you fall in love with me by force. I was trying to make you go away and it didn't work.
21:57
Xue
I don't know why Claire is being cool anyways in the series.
21:58
Alberta
Because she knows Mikey is still there. The whole thing only works because he doesn't leave. She can be as chaotic as she wants and he absorbs it.
22:00
Which is a terrible dynamic.
22:00
You absorbed a lot too but I'd rather not keep testing that.
22:01
Xue
Sure, you don't have to, so let's just come tomorrow.
22:02
Alberta
Yeah, tomorrow.
22:03
Notes
1. Generated humans - in the world of this story, humans created through accelerated biological maturation in laboratory conditions rather than natural development. They are legally recognized citizens with full rights, though their social and institutional status remains contested throughout the story. ↩
2. Printed generated humans - a later generation of generated humans created through molecular printing rather than biological maturation. Traditional generated humans grow organically in accelerated conditions; printed humans are assembled at the molecular level and may incorporate hardware components at the time of creation. ↩
3. ARM / RISC-V - two families of processor architecture based on the Reduced Instruction Set Computing (RISC) philosophy: fewer, simpler instructions executed very efficiently. ARM is ubiquitous in smartphones and embedded devices; RISC-V is a newer, royalty-free open standard. Both contrast with x86, the complex instruction set architecture used in most personal computers. ↩
4. Occipital lobe - the rearmost region of the cerebral cortex, primarily responsible for visual processing. Its position at the back of the skull and its relatively organized structure make it the site the Institute chose for hardware implantation in the story. ↩
5. Instruction Set Architecture (ISA) - the complete specification of what instructions a processor can execute and how. It defines the "language" of the hardware: what binary patterns mean what operations. Publishing an ISA allows others to write software for, or build compatible hardware around, a processor design. Keeping it proprietary prevents independent analysis. ↩
6. Usage limits (story-specific) - the story borrows this term from AI model rate-limiting, where a language model stops responding after a certain number of interactions. Here it refers to behavioral throttles engineered into the chip: the person becomes progressively less able to sustain social interaction, mirroring how an AI assistant might become unavailable after heavy use. ↩
7. Big Five personality traits - the dominant model in academic personality psychology, describing five broad dimensions: Openness to experience, Conscientiousness, Extraversion, Agreeableness, and Neuroticism (often abbreviated OCEAN). Widely used in research but contested as a complete account of human personality. ↩
8. Bundestag - Germany's federal parliament, the primary legislative body of the Federal Republic. Passes federal law, elects the Chancellor, and exercises budgetary control. In the story's timeline, the Bundestag passed the Generated Human Civil Capacity Protection Act in 2031, granting generated humans full legal personhood and citizenship rights, the legislative foundation for the subsequent court proceedings when those rights are found to have been violated by the Institute's chip program. ↩
9. ReactOS - a free, open-source operating system project attempting to create a binary-compatible replacement for Windows through clean-room reverse engineering. Development began in 1996. As of the story's timeline it remains in alpha and struggles to run reliably on real hardware, which is why Dr. Rainer uses it as an example of a slow, difficult reverse-engineering effort. The Cortex Project later inverts this comparison. ↩
10. Frontiers - an open-access academic publisher founded in Lausanne in 2007, operating a suite of peer-reviewed journals across scientific disciplines. Open-access means the published paper is freely available to anyone without a paywall, a deliberate choice by the Cortex Project, given that their subject is a chip implanted in people who have a direct interest in reading the findings. Frontiers in Neuroscience and Frontiers in Computer Science both cover the paper's interdisciplinary scope. ↩
11. HAL_ABUS (story-specific) - Hardware Abstraction Layer Analog Bus: the name the Cortex Project gives to the physical connection between the chip and biological neural tissue. Unlike a digital bus, it carries analog electrical signals in the millivolt range, matched to the characteristics of biological neurons. ↩
12. Local Field Potential (LFP) - a measure of the summed electrical activity of many neurons in a small brain region, recorded by electrodes placed in or near tissue. Used in neuroscience research and neural prosthetics to read brain signals. The Ljubljana researchers' independent measurement of a 106-microsecond LFP response at 65 Hz confirms the Cortex Project's findings from the opposite direction. ↩
13. Itanium - Intel's 64-bit RISC processor architecture launched in 2001, developed jointly with HP. Technically sophisticated (128 general-purpose registers, EPIC (Explicitly Parallel Instruction Computing) execution model) but commercially catastrophic. The software ecosystem never followed. Compilers struggled to exploit its parallelism, x86 emulation was slow, and existing software could not be recompiled fast enough to make the transition worthwhile. Intel discontinued it in 2021. In the story it becomes the recurring comparison for the NCA: a technically interesting architecture whose real-world outcome is a graveyard. ↩
14. SPARCstation - a workstation computer manufactured by Sun Microsystems in the late 1980s and 1990s, based on the SPARC (Scalable Processor Architecture) processor. SPARC uses a big-endian register architecture with a distinctive feature called register windows: the available set of registers shifts on function calls. This architectural feature turns out to have a measurable effect on the chip, producing the 106-microsecond response that links digital computing to biological neural timing. ↩
15. Solaris - Sun Microsystems' Unix-based operating system, first released in 1992, now maintained by Oracle. Known for its stability, ZFS filesystem, and DTrace dynamic tracing framework. Runs natively on SPARC hardware. The Cortex Project acquires a SPARCstation 20 and installs Solaris 2.6, the version that shipped with the machine, because the SPARCstation's SBus architecture is the only way to interface directly with the chip's physical layer at the required 3 microsecond jitter tolerance. Solaris 2.6 dates from 1996. ↩
16. DAC - Digital-to-Analog Converter - an electronic component that converts a digital numeric value into a proportional analog voltage or current. In the Cortex Project's context, a DAC is required to produce the 4.42 millivolt, 65 hertz carrier signal that the HAL_ABUS interface expects. The MCP4725 used in the lab is a small, inexpensive I²C DAC commonly found in hobbyist electronics. Connecting it to the chip's four analog contact pads allows the team to send controlled signals directly to the interface, the only way to test whether the chip responds without access to a living neural substrate. ↩
17. ESR meter - Equivalent Series Resistance meter. An instrument that measures the internal resistance of capacitors. A healthy capacitor has very low ESR; a failing one has high ESR. Visual inspection alone cannot reliably identify failing capacitors - ESR testing reveals degraded components before they fail catastrophically (as one eventually does, explosively, in Chapter VI). ↩
18. NVRAM - Non-Volatile Random-Access Memory. Memory that retains its contents without power. In older Sun workstations like the SPARCstation 20, the NVRAM chip (typically an M48T08 or similar) stores the machine's unique hardware identifier, Ethernet address, and firmware configuration. It contains a small internal battery that degrades over decades. ↩
19. QNX Neutrino - a real-time operating system (RTOS) used in embedded and industrial systems. Unlike general-purpose operating systems, it provides deterministic timing: when a program requests the CPU at a specific moment, it receives it at that moment without interference from other processes. This is essential for driving the chip's analog interface at precisely 65 hertz. ↩
20. AntiX Linux - a lightweight Linux distribution designed to run on hardware with very limited resources (as little as 192MB of RAM). It omits the graphical overhead of mainstream distributions, making it the practical choice for old, underpowered, or donated machines - which describes every computer in the Siedlischte lab. ↩
21. x86-64 (AMD64) - the 64-bit extension of Intel's original x86 instruction set, developed by AMD in 2000 and later adopted by Intel under the name Intel 64. The dominant instruction set architecture for desktop and server computing. Defined by a register file of 16 general-purpose 64-bit registers, variable-length instruction encoding, and decades of backward compatibility with 32-bit and 16-bit x86 code. The Cortex Project identifies the chip's external ISA presentation as modified x86-64, familiar enough to be measurable with standard tools, different enough to hide the HAL_ABUS interface from casual inspection. ↩
22. FSFE - Free Software Foundation Europe - an independent non-profit organisation founded in 2001, promoting free software and digital rights across Europe. Distinct from the US-based FSF, though aligned in values. Campaigns include "Public Money, Public Code", the principle that software developed with public funding should be released as free software. The Institute of Genetics cites FSFE directly in the Symposium presentation when justifying why the ISA remains proprietary despite being publicly funded, which is a precise inversion of the argument FSFE actually makes. ↩
23. The four freedoms (FSF) - the Free Software Foundation's definition of software freedom: (0) the freedom to run the software for any purpose; (1) to study how it works and modify it; (2) to redistribute copies; (3) to distribute modified versions. These freedoms require access to source code. The Institute's spokesperson's statement that it has "never granted" these freedoms to generated humans is described in court as "a precise and accurate description of the wrong being committed." ↩
24. CCC - Chaos Computer Club - Europe's largest and oldest hacker association, founded in Hamburg in 1981. Defines hacking in the exploratory and civic sense: understanding how systems work, exposing security vulnerabilities, and advocating for digital rights and open access to information. The Hamburg chapter is among the most active. The CCC has a long history of hardware reverse engineering and has presented findings on proprietary systems at its annual Chaos Communication Congress events. ↩
25. Digitalcourage e.V. - a German civil rights organisation focused on data protection and digital rights, founded in Bielefeld in 1987 (originally as FoeBuD). Operates the Big Brother Awards Germany, which annually names the worst privacy offenders in the country. Files complaints with data protection authorities on behalf of affected individuals. The 'e.V.' designation (eingetragener Verein) indicates a registered non-profit association under German law. ↩
26. GDPR, General Data Protection Regulation - EU Regulation 2016/679, in force since 2018. Governs the collection, processing, and storage of personal data within the EU and EEA. Establishes rights for data subjects (access, erasure, portability) and obligations for controllers. Article 9 covers special categories of sensitive data including health and biometric data; Article 35 requires a Data Protection Impact Assessment before high-risk processing begins. Violations carry fines of up to 4% of global annual turnover or €20 million, whichever is higher. The NCA's HAL_ABUS interface, capable of processing neurological data, places it squarely within GDPR's scope, a fact Intel's communications team is actively not discussing. ↩
27. Verwaltungsgericht - German administrative court. Germany maintains a parallel court system specifically for disputes between citizens and government institutions, separate from criminal and civil courts. Cases involving publicly funded institutions, government decisions, and constitutional rights go to these courts. ↩
28. Grundgesetz - the Basic Law, Germany's constitution, enacted in 1949. Article 2(2) guarantees the inviolability of physical integrity: "Every person shall have the right to life and physical inviolability." The plaintiffs argue that implanting a device with an undisclosed operational specification violates this right on an ongoing basis. ↩
29. Öffentlichkeitspflicht - literally "public accountability obligation". The legal principle in German administrative law that publicly funded institutions must be transparent about their activities, decisions, and research outputs. The plaintiffs argue this requires the Institute to disclose an instruction set developed entirely with public funding. ↩
30. Clean-room design - a legal methodology for creating compatible software or hardware without infringing copyright. Two teams are strictly separated by an information barrier: Team A documents observed behavior of the proprietary original without accessing its internal code while Team B writes a new implementation using only Team A's documentation. Because Team B never saw the original, their work is legally independent. The Cortex Project applies this methodology to create OpenCortex. ↩
31. Coreboot - free and open-source firmware that replaces proprietary BIOS/UEFI. It initializes the processor and memory at startup, then hands control to a small program called a "payload" which loads the operating system. Using coreboot means OpenCortex initialization runs on hardware without Intel's proprietary firmware layer in between. ↩
32. LLVM - a compiler infrastructure project that separates the front end (parsing a programming language) from the back end (generating machine code for a specific processor). Writing an LLVM backend for OpenCortex would allow any LLVM-supported language (C, C++, Rust, Swift, and many others) to compile to OpenCortex instructions without any changes to the language itself. ↩
33. IDT (Interrupt Descriptor Table) - a data structure used by x86 processors to map interrupt numbers to handler functions. Entry 6 is permanently assigned to the Invalid Opcode exception (#UD). By installing their own handler at IDT entry 6, OpenCortex intercepts every unrecognized instruction before it crashes the system, allowing OpenCortex mnemonics to execute as if the processor natively supported them. ↩
34. Wohlerspark - a public park in the Altona-Altstadt district of Hamburg, formerly the Norderreihe cemetery, established 1831 and active until 1945. Converted to parkland in 1979. The old gravestones were left in place along the paths and edges rather than removed, giving the park its distinctive atmosphere: linden alleys, weathered stone, names worn to near-illegibility. Known locally as a quiet, slightly contemplative space. The story uses it as the primary outdoor meeting location for Xue and Alberta - a place that has been repurposed without erasing what it was. ↩
35. Thermal envelope (TDP) - the maximum heat a processor generates under load, measured in watts. Datacenter processors typically have TDPs of 200-400 watts and require active cooling. A passively cooled chip is limited to around 10-15 watts. The NCA's passive cooling design reveals it was not built to perform the intensive computation a datacenter chip is expected to perform. ↩
36. Integrated Heat Spreader (IHS) - the metal lid on the top of a CPU die that spreads heat from the small silicon chip across a larger surface for more efficient cooling. On a standard Intel processor the IHS bears the product name and specifications. The NCA's blank, anomalously light IHS suggests a different thermal design and a deliberate choice to leave the top surface unmarked. ↩
37. LGA (Land Grid Array) - a processor socket design where the electrical contacts are on the motherboard rather than the chip. High-end server sockets like LGA 4677 have 4,677 contacts. The NCA's three-sided partial contact array is a significant departure, incompatible with any existing motherboard. ↩
38. Intel Centrino - a brand of mobile processor platform launched by Intel in 2003, combining a low-power CPU with integrated wireless networking. The Centrino was notable for its small physical footprint and efficient power use, making it the dominant laptop chip of its era. Its compact form factor is what Xue is comparing to the NCA in the server shop. ↩
39. EMI compliance - Electromagnetic Interference compliance testing, required for all electronic equipment sold in the EU and most markets. Tests measure unintentional electromagnetic emissions at various frequencies. The HAL_ABUS carrier at 4.42 millivolts and 65 hertz is far below standard EMI detection thresholds, meaning a device containing it would pass certification without the analog bus ever being identified. ↩
40. Hacker News - a technology-focused news aggregator and discussion forum operated by Y Combinator. Known for its technically literate community, upvote-ranked submissions, and comment threads that frequently include domain experts. A story reaching the front page of Hacker News is a reliable signal that it has penetrated the global technology community. In the story, multiple Cortex Project developments break into wider public consciousness via Hacker News first. ↩
41. X11 (X Window System) - the foundational display server protocol for Unix and Linux graphical interfaces, developed at MIT in 1984. Provides the network-transparent windowing layer that desktop environments like GNOME and KDE run on top of. X11 has been the standard for decades but carries significant architectural legacy: it was designed for a network computing model that no longer reflects how most desktops are used, and its security model makes certain modern features difficult to implement cleanly. ↩
42. Wayland - a modern display server protocol designed to replace X11, with development starting in 2008. Simpler architecture, better security isolation between applications, and native support for modern graphics features like smooth compositing and HDR. The migration from X11 to Wayland has been gradual and sometimes painful. Screen sharing, remote desktop, and some legacy applications required significant work to function correctly. By the story's timeline, Wayland is the default on most major Linux distributions, though X11 compatibility layers remain common. ↩
43. Trisquel - a fully free GNU/Linux distribution based on Ubuntu, containing very little to no proprietary software or firmware blobs. Ships with only free-software components, which means no proprietary drivers, no non-free codecs, and no binary firmware for hardware that requires it. Alberta's laptop comes with it preinstalled, an unusual manufacturer choice that implies either a deliberate values decision or a very specific hardware configuration that needs no proprietary components. ↩
44. NCAC, Neural Compute Architecture Consortium - the proprietary licensing body formed by Intel, Microsoft, Google DeepMind, IBM, SAP, and Qualcomm in response to the court proceedings and community pressure. Consortium members gain access to the full ISA documentation under shared proprietary terms. The structure is designed to satisfy the 'spirit' of the court's disclosure order, making the ISA accessible to a broad group, while keeping it out of the public domain and away from open-source licensing. ↩
45. Eingetragene Genossenschaft (eG) - a registered cooperative under German law. A democratic legal entity where each member holds one vote regardless of financial contribution. Unlike a company, its purpose is to serve its members rather than maximize profit. This structure makes Stronk's one-euro membership and majority-rules governance legally coherent, and makes it considerably harder to acquire or take over than a standard corporation. ↩
46. Ciao stronzi - Italian: roughly 'goodbye, assholes'. A colloquial dismissal, profane but not violently so. The cooperative used it as a founding statement of intent, addressed to the assembled large technology corporations in its legally filed articles of association. It is not the first time a serious political or legal document has opened with profanity. It is perhaps the first time one has been filed with the Handelsregister Hamburg. ↩
47. CJEU, Court of Justice of the European Union - the EU's highest court, based in Luxembourg. When a national court encounters a question of EU law not yet definitively answered, it refers the question to the CJEU for a binding ruling that applies across all member states. A referral typically takes 18 months to 3 years to resolve, making it both a powerful legal tool and a significant source of delay in the proceedings. ↩
48. GNU General Public License version 3 (GPL v3) - the most widely used copyleft software license, written by the Free Software Foundation. Its key provision: anyone distributing GPL v3 software must also make the source code available under the same license. Unlike permissive licenses, it is designed to be sticky as modifications and derived works must remain free. Releasing the ISA under GPL v3 would mean Intel and every consortium member could still use it, but could not keep their implementations proprietary. ↩
49. Article 101 TFEU - a provision of the Treaty on the Functioning of the European Union that prohibits agreements between companies restricting or distorting competition within the EU internal market. Joint licensing arrangements that lock out competitors can fall within its scope. Enforced by the European Commission's Directorate-General for Competition, with fines of up to 10% of global annual turnover. ↩
50. Microsoft BUILD - Microsoft's annual developer conference, where the company announces new platforms, tools, and strategic directions to software developers. Historically held in Seattle or Redmond. Known for product launches, API announcements, and keynotes that set the tone for Microsoft's priorities for the year. In the story's timeline, BUILD 2036 is where Brad Mercer publicly addresses the Stronk situation and announces Windows 12's neural compute integration layer for enterprise. ↩